MT9196 Mitel Semiconductor, MT9196 Datasheet - Page 20

• Manufacturer Part Number: MT9196
• Description: Integrated Digital Phone Circuit (IDPC)
• Manufacturer: Mitel Semiconductor

MT9196
Note: Bits marked "-" are reserved bits and should be written with logic "0".
7-146
FDI Control Register
Watchdog Register
ST-BUS/SSI
CEN
DEN
D8
Asynch/Synch,
CSL
1
,CSL
0
Note: Asynch/Synch must be set low for ST-BUS operation
Asynch/Synch
-
-
7
7
1
1
0
0
0
0
When high, the FDI port operates in ST-BUS mode. When low, the FDI operates in SSI mode.
When high, data written into the C-Channel register (address 14h) are transmitted during channel 1 on DSTo.
When high, data written into the D-Channel Register (address 15h) are transmitted during channel 0 on DSTo.
When high, the D-Channel operates at 8 kb/s.
When low, the D-Channel operates at 16 kb/s default.
When low, the channel 1 timeslot is tri-stated on DSTo. Channel 1 data received on DSTi is read via the C-
Channel register (address 14h) regardless of the state of CEN. This control bit has significance only for ST-BUS
operation and is ignored for SSI operation.
When low, the channel 0 timeslot is tri-stated on DSTo. Channel 0 data received on DSTi is read via the D-
Channel register regardless of the state of DEN. This control bit has significance only for ST-BUS mode and is
ignored for SSI operation.
Control bits Asynch/Synch, CSL
following table (CSL
ST-BUS/
SSI
-
6
6
CEN
CSL
0
0
0
0
1
1
-
5
5
1
1
and CSL
DEN
CSL
0
4
4
0
1
0
1
0
1
0
0
are ignored in ST-BUS mode):
1
D8
and CSL
1
3
3
Bit Clock Rate (kHz)
Asynch/
Synch
0
are used to program the data clock (BCL) bit rates as shown in the
0
2
2
1536
2048
4096
128
256
512
CSL
1
1
1
1
ADDRESS = 10h WRITE/READ VERIFY
CSL
0
0
0
0
Preliminary Information
CLOCKin (kHz)
4096 mandatory
4096 mandatory
ADDRESS = 11h WRITE
1536
2048
4096
512
Power Reset Value
Power Reset Value
X000 0000
XXXX XXXX