MT8889CC_CC-1

Manufacturer Part NumberMT8889CC_CC-1
Description6V 10mA integrated DTMF transceiver with adaptive micro interface. For paging systems, repeater systems/mobile radio, credit card systems, personal computers, interconnect dialers
ManufacturerMitel Semiconductor
MT8889CC_CC-1 datasheet
 


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The adaptive micro interface provides access to five
internal registers. The read-only Receive Data
Register contains the decoded output of the last
valid DTMF digit received. Data entered into the
write-only Transmit Data Register will determine
which tone pair is to be generated (see Table 1 for
coding details). Transceiver control is accomplished
with two control registers (see Tables 6 and 7), CRA
and CRB, which have the same address. A write
operation to CRB is executed by first setting the
most significant bit (b3) in CRA. The following write
operation to the same address will then be directed
to CRB, and subsequent write cycles will be directed
back to CRA. The read-only status register indicates
the current transceiver state (see Table 8).
A software reset must be included at the beginning
of all programs to initialize the control registers upon
power-up or power reset (see Figure 15). Refer to
Tables 4-7 for bit descriptions of the two control
registers.
The multiplexed IRQ/CP pin can be programmed to
generate an interrupt upon validation of DTMF
signals or when the transmitter is ready for more
data (burst mode only). Alternatively, this pin can be
configured to provide a square-wave output of the
call progress signal. The IRQ/CP pin is an open drain
output and requires an external pull-up resistor (see
Figure 13).
MC6800/6802
MT8889/MT8889C-1
A0-A15
VMA
D0-D3
RW
2
(a)
MC6809
MT8889/MT8889C-1
A0-A15
Q
E
D0-D3
R/W
Figure 12 a) & b) - MT8889 Interface Connections for Various Intel and Motorola Micros
Motorola
RS0
R/W
0
0
0
1
1
0
1
1
Table 3. Internal Register Functions
b3
RSEL
b3
C/R
MC68HC11
A8-A15
CS
RS0
AS
D0-D3
AD0-AD3
DS
R/W/WR
DS/RD
RW
8031/8051
8080/8085
CS
A8-A15
RS0
ALE
D0-D3
P0
R/W/WR
RD
DS/RD
WR
MT8889C/MT8889C-1
Intel
WR
RD
FUNCTION
0
1
Write to Transmit
Data Register
1
0
Read from Receive
Data Register
0
1
Write to Control Register
1
0
Read from Status Register
b2
b1
b0
IRQ
CP/DTMF
TOUT
Table 4. CRA Bit Positions
b2
b1
b0
S/D
TEST
BURST
ENABLE
Table 5. CRB Bit Positions
MT8889C/MT8889C-1
CS
D0-D3
RS0
DS/RD
R/W/WR
MT8889C/MT8889C-1
CS
D0-D3
RS0
DS/RD
R/W/WR
(b)
4-115