CS4336 Cirrus Logic, CS4336 Datasheet - Page 11

• Manufacturer Part Number: CS4336
• Description: (CS4334 - CS4339) Stereo D/A Converter
• Manufacturer: Cirrus Logic

3. GENERAL DESCRIPTION
The CS4334 family of devices offers a complete
stereo digital-to-analog system including digital in-
terpolation, fourth-order delta-sigma digital-to-an-
alog conversion, digital de-emphasis and analog
filtering, as shown in Figure 8. This architecture
provides a high tolerance to clock jitter.
The primary purpose of using delta-sigma modula-
tion techniques is to avoid the limitations of resis-
tive laser trimmed digital-to-analog converter
architectures by using an inherently linear 1-bit
digital-to-analog converter. The advantages of a 1-
bit digital-to-analog converter include: ideal differ-
ential linearity, no distortion mechanisms due to re-
sistor matching errors and no linearity drift over
time and temperature due to variations in resistor
values.
The CS4334 family of devices supports two modes
of operation. The devices operate in Base Rate
Mode (BRM) when MCLK/LRCK is 256, 384 or
512 and in High Rate Mode (HRM) when
MCLK/LRCK is 128 or 192. High Rate Mode al-
lows input sample rates up to 100 kHz.
3.1 Digital Interpolation Filter
The digital interpolation filter increases the sample
rate, Fs, by a factor of 4 and is followed by a
32× digital sample-and-hold (16× in HRM). This
DS248PP3
Digital
Input
Interpolator
Delta-Sigma
Modulator
Figure 8. System Block Diagram
filter eliminates images of the baseband audio sig-
nal which exist at multiples of the input sample
rate. The resulting frequency spectrum has images
of the input signal at multiples of 4 Fs. These imag-
es are easily removed by the on-chip analog low-
pass filter and a simple external analog filter (see
Figure 7).
3.2 Delta-Sigma Modulator
The interpolation filter is followed by a fourth or-
der delta-sigma modulator which converts the in-
terpolation filter output into 1-bit data at a rate of
128 Fs in BRM (or 64 Fs in HRM).
3.3 Switched-Capacitor DAC
The delta-sigma modulator is followed by a digital-
to-analog converter which translates the 1-bit data
into a series of charge packets. The magnitude of
the charge in each packet is determined by sam-
pling of a voltage reference onto a switched capac-
itor, where the polarity of each packet is controlled
by the 1-bit data. This technique greatly reduces the
sensitivity to clock jitter and provides low-pass fil-
tering of the output.
3.4 Analog Low-Pass Filter
The final signal stage consists of a continuous-time
low-pass filter which serves to smooth the output
and attenuate out-of-band noise.
DAC
Low-Pass
Analog
Filter
CS4334/5/6/7/8/9
Analog
Output
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