AD9520 Analog Devices, Inc., AD9520 Datasheet - Page 35

no-image

AD9520

Manufacturer Part Number
AD9520
Description
12 Lvpecl/24 Cmos Output Clock Generator
Manufacturer
Analog Devices, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9520-1BCPZ
Manufacturer:
ADI
Quantity:
27
Part Number:
AD9520-1BCPZ
Manufacturer:
Analog Devices Inc
Quantity:
135
Part Number:
AD9520-2BCPZ
Manufacturer:
Analog Devices Inc
Quantity:
135
Part Number:
AD9520-4BCPZ
Manufacturer:
Nuvoton
Quantity:
587
Part Number:
AD9520-4BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD9520-4BCPZ-REEL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD9520-5BCPZ
Manufacturer:
Analog Devices Inc
Quantity:
135
External/Manual Holdover Mode
A manual holdover mode can be enabled that allows the user to
place the charge pump into a high impedance state when the
SYNC pin is asserted low. This operation is edge sensitive, not
level sensitive. The charge pump enters a high impedance state
immediately. To take the charge pump out of a high impedance
state, take the SYNC pin high. The charge pump then leaves the
high impedance state synchronously with the next PFD rising
edge from the reference clock. This prevents extraneous charge
pump events from occurring during the time between SYNC
going high and the next PFD event. This also means that the
charge pump stays in a high impedance state if there is no
reference clock present.
The B counter (in the N divider) is reset synchronously with the
charge pump, leaving the high impedance state on the reference
path PFD event. This helps align the edges out of the R and N
dividers for faster settling of the PLL. Because the prescaler is
not reset, this feature works best when the B and R numbers are
close because this results in a smaller phase difference for the
loop to settle out.
Rev. 0 | Page 35 of 80
When using this mode, the channel dividers should be set to ignore
the SYNC pin (at least after an initial SYNC event). If the dividers
are not set to ignore the SYNC pin, any time SYNC is taken low
to put the part into holdover, the distribution outputs turn off.
The channel divider ignore SYNC function is found in 0x191[6],
0x194[6], 0x197[6], and 0x19A[6] for Channel Divider 0, Channel
Divider 1, Channel Divider 2, and Channel Divider 3, respectively.
Automatic/Internal Holdover Mode
When enabled, this function automatically puts the charge
pump into a high impedance state when the loop loses lock.
The assumption is that the only reason the loop loses lock is due
to the PLL losing the reference clock; therefore, the holdover
function puts the charge pump into a high impedance state to
maintain the VCO frequency as close as possible to the original
frequency before the reference clock disappeared.
A flowchart of the automatic/internal holdover function
operation is shown in Figure 34.
AD9520-5

Related parts for AD9520