AD9520 Analog Devices, Inc., AD9520 Datasheet - Page 70

• Manufacturer Part Number: AD9520
• Description: 12 Lvpecl/24 Cmos Output Clock Generator
• Manufacturer: Analog Devices, Inc.

Reg.
Addr
(Hex) Bit(s) Name
190
190
191
191
191
191
191
192
192
192
AD9520-5
Reg.
Addr
(Hex) Bit(s) Name
0FC
0FC
0FC
0FC
0FC
0FC
0FC
0FD
0FD
0FD
0FD
Table 50. LVPECL Channel Dividers
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
[7:4]
[3:0]
[7]
[6]
[5]
[4]
[3:0]
[2]
[1]
[0]
CSDLD En OUT6 OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT5 OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT4 OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT3 OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT2 OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT1 OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT0 OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En
OUT11
CSDLD En
OUT10
CSDLD En OUT9 OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT8 OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Divider 0 low cycles
Divider 0 high cycles
Divider 0 bypass
Divider 0 ignore SYNC
Divider 0 force high
Divider 0 start high
Divider 0 phase offset
Channel 0 power-down
Channel 0 direct-to-output
Disable Divider 0 DCC
Description
OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Description
Number of clock cycles (minus 1) of the divider input during which the divider output stays
low. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x7).
Number of clock cycles (minus 1) of the divider input during which the divider output stays
high. A value of 0x7 means that the divider is high for eight input clock cycles (default: 0x7).
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
Phase offset (default: 0x0).
Channel 0 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT0/OUT0, OUT1/OUT1, and OUT2/OUT2 are put into safe power-
down mode by setting this bit.)
Connects OUT0, OUT1, and OUT2 to Divider 0 or directly to CLK.
[1] = 0; OUT0, OUT1, and OUT2 are connected to Divider 0 (default).
[1] = 1;
If 0x1E1[0] = 0, the CLK is routed directly to OUT0, OUT1, and OUT2.
If 0x1E1[0] = 1, there is no effect.
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
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