LT1766 Linear Technology, LT1766 Datasheet - Page 19

• Manufacturer Part Number: LT1766
• Description: 5.5V to 60V 1.5A/ 200kHz Step-Down Switching Regulator
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
Thermal resistance for the LT1766 packages is influenced
by the presence of internal or backside planes.
SSOP (GN16) Package: With a full plane under the GN16
package, thermal resistance will be about 85 C/W.
TSSOP (Exposed Pad) Package: With a full plane under the
TSSOP package, thermal resistance will be about 45 C/W.
To calculate die temperature, use the proper thermal
resistance number for the desired package and add in
worst-case ambient temperature:
When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power:
Only a portion of the temperature rise in the external
inductor and diode is coupled to the junction of the LT1766.
Based on empirical measurements the thermal effect on
LT1766 junction temperature due to power dissipation in
the external inductor and catch diode can be calculated as:
Using the example calculations for LT1766 dissipation,
the LT1766 die temperature will be estimated as:
With the GN16 package (
temperature of 60 C:
With the TSSOP package (
temperature of 60 C:
T
V
P
R
P
T
T
T
P
P
J
DIODE
DIODE
J
J
J
F
INDUCTOR
INDUCTOR
L
T
= T
J
= T
= 60 + (85 • 0.53) + (10 • 0.65) = 112 C
= 60 + (45 • 0.53) + (10 • 0.65) = 90 C
= Forward voltage of diode (assume 0.63V at 1A)
= Inductor DC resistance (assume 0.1 )
(LT1766) (P
A
A
+ (
+ (
( )(
( . )(
0 63 40 5 1
V V
= (I
(1)
JA
JA
F
2
LOAD
• P
• P
(0.1) = 0.1W
IN
U
40
TOT
TOT
DIODE
–
)
2
V
– )( )
)
V
) + [10 • (P
IN
(R
OUT
U
L
+ P
JA
)
JA
)(
INDUCTOR
I
= 85 C/W), at an ambient
LOAD
= 45 C/W), at an ambient
0 55
.
DIODE
W
)
W
)(10 C/W)
+ P
INDUCTOR
U
)]
Die temperature can peak for certain combinations of V
V
switch AC losses, quiescent and catch diode losses, a
lower V
losses. In general, the maximum and minimum V
should be checked with maximum typical load current for
calculation of the LT1766 die temperature. If a more
accurate die temperature is required, a measurement of
the SYNC pin resistance (to GND) can be used. The SYNC
pin resistance can be measured by forcing a voltage no
greater than 0.5V at the pin and monitoring the pin current
over temperature in an oven. This should be done with
minimal device power (low V
(V
ambient (oven) temperature.
Note: Some of the internal power dissipation in the IC, due
to BOOST pin voltage, can be transferred outside of the IC
to reduce junction temperature, by increasing the voltage
drop in the path of the boost diode D2 (see Figure 9). This
reduction of junction temperature inside the IC will allow
higher ambient temperature operation for a given set of
conditions. BOOST pin circuitry dissipates power given
by:
Typically V
equals Vout. This is because diodes D1 and D2 can be
considered almost equal, where:
Hence the equation used for boost circuitry power dissipa-
tion given in the previous Thermal Calculations section is
stated as:
Here it can be seen that boost power dissipation increases
as the square of V
V
the voltage drop in the path of D2. Care should be taken
that V
OUT
C2
C
V
P
P
= 0V)) in order to calibrate SYNC pin resistance with
C2
DISS BOOST
DISS BOOST
below V
and load current. While higher V
C2
= V
IN
(
(
does not fall below the minimum 3.3V boost
may generate greater losses due to switch DC
OUT
C2
OUT
(the boost voltage across the capacitor C2)
– V
)
)
to save power dissipation by increasing
FD2
OUT
V
V
OUT
OUT
– (–V
. It is possible, however, to reduce
• (
• (
LT1766/LT1766-5
I
I
FD1
SW
SW
V
V
IN
) = V
IN
/
/
36
36
IN
)•
OUT
) •
and no switching
V
V
OUT
C
IN
2
gives greater
IN
19
levels
1766fa
IN
,