MC14013BCPG ON Semiconductor, MC14013BCPG Datasheet

IC FLIP FLOP DUAL TYPE D 14DIP

MC14013BCPG

Manufacturer Part Number
MC14013BCPG
Description
IC FLIP FLOP DUAL TYPE D 14DIP
Manufacturer
ON Semiconductor
Series
4000Br
Type
D-Typer
Datasheets

Specifications of MC14013BCPG

Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
14MHz
Delay Time - Propagation
50ns
Trigger Type
Positive Edge
Voltage - Supply
3 V ~ 18 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Through Hole
Package / Case
14-DIP (0.300", 7.62mm)
Number Of Circuits
2
Logic Family
MC140
Logic Type
D-Type Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
350 ns
High Level Output Current
- 4.2 mA
Low Level Output Current
4.2 mA
Supply Voltage (max)
18 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 55 C
Supply Voltage (min)
3 V
Circuit Type
Low-Power Schottky
Current, Supply
120 μA
Function Type
D-Type
Logic Function
Flip-Flop
Package Type
PDIP-14
Temperature, Operating, Range
-55 to +125 °C
Voltage, Supply
3 to 18 VDC
Technology
CMOS
Number Of Bits
2
Number Of Elements
2
Clock-edge Trigger Type
Positive-Edge
Operating Supply Voltage (typ)
3.3/5/9/12/15V
Frequency (max)
7MHz
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
18V
Operating Temp Range
-55C to 125C
Operating Temperature Classification
Military
Mounting
Through Hole
Pin Count
14
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output High, Low
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
MC14013BCPGOS
MC14013B
Dual Type D Flip−Flop
The MC14013B dual type D flip−flop is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each flip−flop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q). These devices may be used as shift register
elements or as type T flip−flops for counter and toggle applications.
Features
Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge−Clocked Flip−Flop Design
Logic state is retained indefinitely with clock level either high or
low; information is transferred to the output only on the
positive−going edge of the clock pulse
Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
Pin−for−Pin Replacement for CD4013B
Pb−Free Packages are Available
MAXIMUM RATINGS
(Voltages Referenced to V
Symbol
Parameter
V
DC Supply Voltage Range
DD
V
, V
Input or Output Voltage Range
in
out
(DC or Transient)
I
, I
Input or Output Current
in
out
(DC or Transient) per Pin
P
Power Dissipation, per Package
D
(Note 1)
T
Ambient Temperature Range
A
T
Storage Temperature Range
stg
T
Lead Temperature
L
(8−Second Soldering)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
v (V
or V
) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
or V
). Unused outputs must be left open.
SS
DD
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 7
)
SS
Value
Unit
−0.5 to +18.0
V
−0.5 to V
+ 0.5
V
DD
± 10
mA
500
mW
−55 to +125
°C
−65 to +150
°C
260
°C
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
and V
should be constrained
in
out
1
http://onsemi.com
MARKING
DIAGRAMS
14
PDIP−14
MC14013BCP
P SUFFIX
AWLYYWWG
CASE 646
1
14
SOIC−14
14013BG
D SUFFIX
AWLYWW
CASE 751A
1
14
14
TSSOP−14
013B
DT SUFFIX
ALYW G
CASE 948G
G
1
14
SOEIAJ−14
MC14013B
F SUFFIX
ALYWG
CASE 965
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Publication Order Number:
MC14013B/D

Related parts for MC14013BCPG

MC14013BCPG Summary of contents

Page 1

MC14013B Dual Type D Flip−Flop The MC14013B dual type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each flip−flop has independent Data, (D), Direct Set, (S), Direct Reset, (R), and Clock ...

Page 2

... ORDERING INFORMATION Device MC14013BCP MC14013BCPG MC14013BD MC14013BDG MC14013BDR2 MC14013BDR2G MC14013BDTR2 MC14013BDTR2G MC14013BF MC14013BFG MC14013BFEL MC14013BFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. ...

Page 3

ELECTRICAL CHARACTERISTICS Î Î Î Î Î ...

Page 4

SWITCHING CHARACTERISTICS Î Î Î Î Î ...

Page 5

D 50% 10 ( PLH 90% 50% Q 10% t TLH Inputs R and S low. Figure 1. Dynamic Signal Waveforms (Data, ...

Page 6

−T− SEATING PLANE 0.13 (0.005) PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE http://onsemi.com 6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI ...

Page 7

... G −T− SEATING 14 PL PLANE 0.25 (0.010 14X 0.58 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE 0.25 (0.010 ...

Page 8

... S A −V− C 0.10 (0.004) −T− SEATING G D PLANE 14X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE 0.25 (0.010) ...

Page 9

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

Related keywords