LTC2492 Linear Technology, LTC2492 Datasheet - Page 14

• Manufacturer Part Number: LTC2492
• Description: 24-Bit 2-/4-Channel ADC
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
LTC2492
CONVERTER OPERATION
Converter Operation Cycle
The LTC2492 is a multi-channel, low power, delta-
sigma analog-to-digital converter with an easy to use
4-wire interface and automatic differential input current
cancellation. Its operation is made up of four states (See
Figure 2). The converter operating cycle begins with the
conversion, followed by the sleep state and ends with the
data input/output cycle. The 4-wire interface consists of
serial data output (SDO), serial clock (SCK), chip select
(CS) and serial data input (SDI).The interface, timing,
operation cycle, and data output format is compatible with
Linear’s entire family of SPI Δ∑ converters.
Initially, at power up, the LTC2492 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, if CS is HIGH, power
consumption is reduced by two orders of magnitude. The
part remains in the sleep state as long as CS is HIGH. The
conversion result is held indefi nitely in a static shift register
while the part is in the sleep state.
Once CS is pulled LOW, the device powers up, exits the
sleep state, and enters the data input/output state. If CS
is brought HIGH before the fi rst rising edge of SCK, the
device returns to the sleep state and the power is reduced.
If CS is brought HIGH after the fi rst rising edge of SCK, the
14
Figure 2. LTC2492 State Transition Diagram
CONFIGURATION SELECT
IN
CHANNEL SELECT
+
DATA OUTPUT
= CH0, IN
POWER UP
50/60Hz,1X
CONVERT
CS = LOW
SCK
SLEEP
AND
–
= CH1
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data output cycle is aborted and a new conversion cycle
begins. The data output corresponds to the conversion
just completed. This result is shifted out on the serial
data output pin (SDO) under the control of the serial
clock pin (SCK). Data is updated on the falling edge of
SCK allowing the user to reliably latch data on the rising
edge of SCK (See Figure 3). The confi guration data for
the next conversion is also loaded into the device at this
time. Data is loaded from the serial data input pin (SDI)
on each rising edge of SCK. The data input/output cycle
concludes once 32 bits are read out of the ADC or when
CS is brought HIGH. The device automatically initiates a
new conversion and the cycle repeats.
Through timing control of the CS and SCK pins, the LTC2492
offers several fl exible modes of operation (internal or
external SCK and free-running conversion modes). These
various modes do not require programming and do not
disturb the cyclic operation described above. These modes
of operation are described in detail in the Serial Interface
Timing Modes section.
Ease of Use
The LTC2492 data output has no latency, fi lter settling
delay, or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog inputs is straight forward. Each conversion,
immediately following a newly selected input or mode,
is valid and accurate to the full specifi cations of the
device.
The LTC2492 automatically performs offset and full scale
calibration every conversion cycle independent of the
input channel selected. This calibration is transparent
to the user and has no effect with the operation cycle
described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage variation, input channel,
and temperature drift.
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