LTC2492 Linear Technology, LTC2492 Datasheet - Page 22

• Manufacturer Part Number: LTC2492
• Description: 24-Bit 2-/4-Channel ADC
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
LTC2492
Typically, CS remains LOW during the data output/input
state. However, the data output state may be aborted by
pulling CS HIGH any time between the 1st falling edge
and the 32nd falling edge of SCK (see Figure 7). On the
rising edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge of
SCK, the new input channel is loaded and valid for the next
conversion cycle. If CS goes high between the 8th falling
edge and the 16th falling edge of SCK, the new channel
is still loaded, but the converter confi guration remains
unchanged. In order to program both the input channel
and converter confi guration, CS must go high after the
16th falling edge of SCK (at this point all data has been
shifted into the device).
22
(EXTERNAL)
SDO
SCK
SDI
CS
CONVERSION
Figure 7. External Serial Clock, Reduced Output Data Length and Valid Channel Selection
DON'T CARE
SLEEP
0.1μF
10μF
BIT 31
1
EOC
1
2.7V TO 5.5V
BIT 30
“0”
0
2
0.1V TO V
REFERENCE
ANALOG
INPUTS
VOLTAGE
BIT 29
SIG
EN
3
CC
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24
MSB
SGL
12
13
14
10
11
4
8
9
7
V
REF
REF
CH0
CH1
CH2
CH3
COM
DATA INPUT/OUTPUT
CC
ODD
LTC2492
+
–
5
External Serial Clock, 3-Wire I/O
This timing mode uses a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an externally
generated serial clock (SCK) signal (see Figure 8). CS is
permanently tied to ground, simplifying the user interface
or isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle typically
concludes 4ms after V
SCK at this time determines if SCK is internally generated
or externally applied. In order to enter the external SCK
mode, SCK must be driven LOW prior to the end of the
POR cycle.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller. EOC = 1 while the conversion is in
progress and EOC = 0 once the conversion is complete.
GND
SDO
SCK
SDI
A2
F
CS
O
6
5
6
2
3
1
4
A1
7
4-WIRE
SPI INTERFACE
A0
8
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
BIT 23
CC
exceeds 2V. The level applied to
CONVERSION
DON'T CARE
Hi-Z
SLEEP
2492 F07
2492fb