LTC2492 Linear Technology, LTC2492 Datasheet - Page 21

• Manufacturer Part Number: LTC2492
• Description: 24-Bit 2-/4-Channel ADC
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
External Serial Clock, Single Cycle Operation
This timing mode uses an external serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 6).
The external serial clock mode is selected during the power-
up sequence and on each falling edge of CS. In order to
enter and remain in the external SCK mode of operation,
SCK must be driven LOW both at power up and on each
CS falling edge. If SCK is HIGH on the falling edge of CS,
the device will switch to the internal SCK mode.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is complete and the device is in the sleep
state. Independent of CS, the device automatically enters
the sleep state once the conversion is complete; however,
in order to reduce the power, CS must be HIGH.
(EXTERNAL)
SDO
SCK
SDI
CS
CONVERSION
DON'T CARE
SLEEP
BIT 31
1
EOC
1
BIT 30
Figure 6. External Serial Clock, Single Cycle Operation
“0”
0
0.1μF
10μF
2
2.7V TO 5.5V
BIT 29
SIG
EN
3
0.1V TO V
REFERENCE
ANALOG
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
INPUTS
VOLTAGE
MSB
SGL
4
CC
ODD
5
12
13
14
10
11
8
9
7
V
REF
REF
CH0
CH1
CH2
CH3
COM
A2
CC
6
LTC2492
+
–
A1
7
GND
SDO
SCK
SDI
CS
F
DATA INPUT/OUTPUT
O
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device remains
in the sleep state until the fi rst rising edge of SCK is seen
while CS is LOW. The input data is then shifted in via the
SDI pin on each rising edge of SCK (including the fi rst rising
edge). The channel selection and converter confi guration
mode will be used for the following conversion cycle. If
the input channel or converter confi guration is changed
during this I/O cycle, the new settings take effect on the
conversion cycle following the data input/output cycle.
The output data is shifted out the SDO pin on each falling
edge of SCK. This enables external circuitry to latch the
output on the rising edge of SCK. EOC can be latched on the
fi rst rising edge of SCK and the last bit of the conversion
result can be latched on the 32nd rising edge of SCK. On
the 32nd falling edge of SCK, the device begins a new
conversion and SDO goes HIGH (EOC = 1) indicating a
conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
5
6
A0
3
2
1
4
8
EN2
9
4-WIRE
SPI INTERFACE
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
IM
10
FA
11
BIT 20 BIT 19
FB
12
SPD
13
BIT 18 BIT 17
14
DON'T CARE
LTC2492
BIT 0
32
21
CONVERSION
Hi-Z
2492fb
2492 F06