RM5261-200-QI PMC-Sierra Inc, RM5261-200-QI Datasheet - Page 23

• Manufacturer Part Number: RM5261-200-QI
• Description: RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002241, Issue 1
3.26 Enhanced Write Modes
Figure 7
Figure 8 shows a processor block write using write response pattern DDDD, or code 0, of the boot-
time mode select options.
Figure 8 Processor Block Write
The RM5231 implements two enhancements to the original R4000 write mechanism: Write
Reissue and Pipeline Writes. The original R4000 allowed a write address cycle on the SysAD bus
only once every four SysClock cycles. Hence for a non-block write, this meant that two out of
every four cycles were wait states.
Pipelined write mode eliminates these two wait states by allowing the processor to drive a new
write address onto the bus immediately after the previous data cycle. This allows for higher
SysAD bus utilization. However, at high bus frequencies the processor may drive a subsequent
write onto the bus prior to the time the external agent deasserts WrRdy*, indicating that it can not
accept another write cycle. This can cause the write cycle to be missed.
Write reissue mode is an enhancement to pipelined write mode and allows the processor to reissue
missed write cycles. If WrRdy* is deasserted during the issue phase of a write operation, the cycle
is aborted by the processor and reissued at a later time.
SysAD
SysClock
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
SysAD
SysClock
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Processor Block Read
Read
Addr
Write
Addr
NData
Data0
NData
Data1
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
NData
Data2
NData
Data0
NEOD
Data3
NData
Data1
NData
Data2
Data3
NEOD
Released
23