TM100SV_02L04 TORiSAN, TM100SV_02L04 Datasheet - Page 10

• Manufacturer Part Number: TM100SV_02L04
• Description: LCD_Module
• Manufacturer: TORiSAN

Tottori SANYO Electric Co., Ltd.
[Note 1] In the following timing waveform, the n-th edge of internal imaginary clock tcn,
[Note 1] Please confirm tcj2 (Jitter rate), if tcj1 (P-P of jitter/100cycles) exceeds 300ps.
[Additional explanation]
Data Setup Time
Data Hold Time
INTERFACE (LVDS) SIGNAL TIMING PARAMETERS
CYCLE JITTER of LVDS CLOCK
P-P of jitter / 100 cycles
Jitter rate
change of t
the tcj2(jitter rate) in this limit is 0.4/5=0.08
ns/cycle and larger than 20ps/cycle,normal
function of the LCD module can not be
assured in this case.
CYCLE JITTER of LVDS CLOCK.
According to this diagram, min. t
25.0ns and max. t
0nc and 100nc. The tcj1 in this sphere is
25.42-25.0=0.42ns and out of
SPEC(MAX.300ps). So, it is neccesary to
measure tcj2 and to judge whether it
conform to above specification(20ps/cycle).
PARAMETER
According to the diagram, the largest
Right diagram showes the example of
PARAMETER
where Tin is period of LVDS input clock.
For this imaginary clock edge, data setup time is tsu and data hold time is thd,
respectively.
which is sampling position of LVDS input data signal, is given by:
LVDS Input Clock
LVDS Input Data
tcn = (2n-1) Tin / 14
CLK
is 0.4ns per 5nc. So that,
CLK
SYMBOL
is 25.42ns between
SYMBOL
n-th edge of internal imaginary clock (data sampling position)
tsu
thd
tcj1
tcj2
CLK
MIN
900
900
tcn
MIN
is
-
-
(n=1,2, ~ 7)
tsu
Tin
TM100SV-02L04
thd
TYP
-
-
TYP
-
-
25.6
25.5
25.4
25.3
25.2
25.1
25.0
24.9
MAX
-
-
0
MAX
300
20
CYCLE JITTER of LVDS CLOCK
UNIT
ps
ps
< EXAMPLE >
CYCLE
ps/cycle
100
UNIT
Ver.1
ps
n
at Tin=25ns
Note 1
c (n)
Note 1
Page
NOTE
200
NOTE
9/17