SCANPSC110F National Semiconductor, SCANPSC110F Datasheet - Page 3

• Manufacturer Part Number: SCANPSC110F
• Description: SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port
• Manufacturer: National Semiconductor

TMS
TDI
TDO
TCK
TRST
S
OE
TDO
TDI
TMS
TCK
V
(0–5)
CC
Name
Table of Contents
Active Scan Chain
Level 1 Protocol
Level 2 Protocol
PAD
LSB
MSB
B
L(1–3)
B
L(1–3)
B
B
L(1–3)
L(1–3)
TTL Input w/Pull-Up
Resistor
TTL Input w/Pull-Up
Resistor
TRI-STATEable,
32 mA/64 mA Drive,
Reduced-Swing,
Output
TTL Schmitt Trigger
Input
TTL Input w/Pull-Up
Resistor
TTL Inputs
TTL Input
TRI-STATEable,
24 mA/24 mA
Drive Outputs
TTL Inputs w/Pull-Up
Resistors
TRI-STATEable,
24 mA/24 mA
Drive Outputs
TRI-STATEable,
24 mA/24 mA
Drive Output
Power Supply Voltage
I/O (Note 1)
The Active Scan Chain refers to the scan chain configuration as seen by the test master at a given
moment. When a ’PSC110F is selected with all of its LSPs parked, the active scan chain is the
current scan bridge register only. When a LSP is unparked, the active scan chain becomes: TDI
Table 4 for Unparked configurations of the LSP network.
Level 1 is the protocol used to address a ’PSC110F.
Level 2 is the protocol that is used once a ’PSC110F is selected. Level 2 protocol is IEEE Std.
1149.1 compliant when an individual ’PSC110F is selected.
A one bit register that is placed at the end of each local scan port scan-chain. The PAD bit
eliminates the prop delay that would be added by the ’PSC110F LSPN logic between TDI
TDO
thus allowing data to be scanned at higher frequencies without violating set-up and hold times.
Least Significant Bit, the right-most position in a register (bit 0)
Most Significant Bit, the left-most position in a register
the current ’PSC110F register
(Continued)
L(n+1)
or TDO
& LCC)
2, 3, 4,
18, 23,
16, 20,
17, 22,
(SOIC
5, 6, 7
15,19,
Pin #
8, 28
10
12
13
11
24
27
25
26
9
1
TABLE 1. Glossary of Terms (Continued)
TABLE 2. Detailed Pin Description Table
B
by buffering and synchronizing the TDI
BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP
Controller of the SCANPSC110F Bridge. Also controls sequencing of the TAPs
which are on the three (3) local scan chains.
BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the
’PSC110F through this input pin.
BACKPLANE TEST DATA OUTPUT: This output drives test data from the
’PSC110F and the local TAPs, back toward the scan master controller.
TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock
signal that controls all scan operations of the ’PSC110F and of the three (3)
local scan ports.
TEST RESET: An asynchronous reset signal (active low) which initializes the
’PSC110F logic.
SLOT IDENTIFICATION: The configuration of these six (6) pins is used to
identify (assign a unique address to) each ’PSC110F on the system backplane.
OUTPUT ENABLE for the Local Scan Ports, active low. When high, this
active-low control signal TRI-STATEs all three local scan ports on the
’PSC110F, to enable an alternate resource to access one or more of the three
(3) local scan chains.
TEST DATA OUTPUTS: Individual output for each of the three (3) local scan
ports.
TEST DATA INPUTS: Individual scan data input for each of the three (3) local
scan ports.
TEST MODE SELECT OUTPUTS: Individual output for each of the three (3)
local scan ports. TMS
to be present on a connected TMS input, per the IEEE 1149.1 requirement)
LOCAL TEST CLOCK OUTPUTS: Individual output for each of the three (3)
local scan ports. These are buffered versions of TCK
Power supply pins, 5.0V
3
the local scan ring registers
L
does not provide a pull-up resistor (which is assumed
±
10%.
Description
L
inputs to the falling edge of TCK
a PAD bit
B
.
TDO
B
. Refer to
www.national.com
Ln
and
B
,
B