cy28551 Cypress Semiconductor Corporation., cy28551 Datasheet
cy28551
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cy28551 Summary of contents
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... CY28551 ® and SIS ® PCI REF LINK DOT96 24_48M 48M VDDREF 47 SCLK 46 SDATA 45 VTTPWRG#/PD 44 CPUT0 43 CPUC0 42 VDDCPU 41 CPUT1 CY28551 40 CPUC1 39 VSSCPU 38 **DOC2 37 VSSA 36 VDDA 35 PCIEXT8/CPU_STP# 34 PCIEXC8/PCI_STP# 33 VDDPCIE , CA 95134-1709 • 408-943-2600 Revised July 26, 2006 [+] Feedback ...
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... CPU outputs/100-MHz Differential serial reference clocks. The two multifunction pins are selected by MODE. Default PCIEX8 Intel Type-SR output buffer Ground for PLL. Dynamic Over Clocking pin 0 = normal Frequency will be changed depend on DOC register. Internal 150k pull-down. Ground for outputs. CY28551 Page [+] Feedback ...
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... Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications Internal 150k pull up Intel Type-3A output buffer Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications CPU buffer type CPU buffer type. selection options. Internal 150k pull up CY28551 Page [+] Feedback ...
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... Table 2. The block write and block read protocol is outlined in Table 3, while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Description CY28551 CPU PLL SRC PLL Gear CPU CPU ...
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... Byte Read Protocol Bit Description 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeated start 27:21 Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop CY28551 Page [+] Feedback ...
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... Disable Enable REF0 Output Enable 0 = Disable Enable CPU[T/C]1 Output Enable 0 = Disable (Tri-state Enable CPU[T/C]0 Output Enable 0 = Disable (Tri-state Enable Reserved PCI6_F Output Enable 0 = Disable Enable PCI5 Output Enable 0 = Disable Enable PCI4 Output Enable 0 = Disable Enable CY28551 Description Description Description Page [+] Feedback ...
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... Allow control of CPU0 with assertion of CPU_STP Free Running 1 = Stopped with CPU_STP# Allow control of PCI6_F with assertion of PCI_STP Free Running 1 = Stopped with PCI_STP# Allow control of PCIEX with assertion of PCI_STP Free Running 1 = Stopped with PCI_STP# SW Frequency selection bits. See Table 1. CY28551 Description Description Description Page [+] Feedback ...
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... FSA Reflects the value of the FSA pin sampled on power up FSA was LOW during VTT_PWRGD# assertion Power Status bit Internal power or Internal resets are NOT valid 1 = Internal power and Internal resets are valid Read only Bit 7 sets to 0 when Bit Description Vendor ID Bit 3 Vendor ID Bit 2 CY28551 Page [+] Feedback ...
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... The DF2_N[8:0] configures CPU frequency for Dynamic Frequency. DOC[1:2] =10 The DF1_N[8:0] configures CPU frequency for Dynamic Frequency. DOC[1:2] =01 RESERVED, Set = 0 RESERVED, Set = 0 Smooth switch Bypass 0 = Activate SMSW block 1 = Bypass and deactivate SMSW block. Smooth switch select 0 = Select CPU_PLL 1 = Select SRC_PLL RESERVED, Set = 0 CY28551 Page [+] Feedback ...
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... The DF2_N[8:0] configures CPU frequency for Dynamic Frequency. DOC[1:2] =10 Description The DF3_N[8:0] configures CPU frequency for Dynamic Frequency. DOC[1:2] =11 Description restored once the system is rebooted 0 = Use HW settings 1 = Recovery N[8:0] Timer_SEL selects the WD reset function at SRESET pin when WD times out Reset and Reload Recovery_Frequency 1 = Only Reset CY28551 Page [+] Feedback ...
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... The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[E:A] register will be used. When it is set, the frequency ratio stated in the FSEL[3:0] register will be used. CY28551 Page [+] Feedback ...
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... Programmable CPU Frequency Enable 0 = Disable Enable Watchdog Autorecovery Mode 0 = Disable (Manual), 1= Enable (Auto) Watchdog Recovery Bit Drive Shunt Cap Motional (max.) (max.) (max 0 0.016 pF CY28551 Description Description Description Tolerance Stability Aging (max.) (max.) (max.) 35 ppm 30 ppm 5 ppm Page [+] Feedback ...
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... Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.) Multifunction Pin Selection In the CY28551, some of the pins can provide different types of frequency, depending on the SEL[1:0] HW strapping pin setting, to support different chipset vendors. The configuration is shown as follows: LINK/DOT/SA ...
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... PLL via SMBUS. By default the smooth switch circuit is set to auto mode. Either PLL can still be overclocked when it does not have control of the smooth switch circuit, but it is not guaranteed to transition to the new frequency without large frequency glitches. CY28551 Page [+] Feedback ...
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... SRESET# pulse after a Watchdog timer time out. After the SRESET# pulse is asserted the SW_RESET bit will be automatically cleared by the device. PD Clarification The VTT_PWRGD#/PD pin is a dual-function pin. During initial power up, the pin functions as VTT_PWRGD#. Once CY28551 Page [+] Feedback ...
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... Figure example showing the relationship of clocks coming up. Unfortunately, we can not show all possible combinations; designers need to ensure that from the first active clock output to the last takes no more than two full PCI clock cycles. Figure 3. PD Assertion Timing Waveform CY28551 Page [+] Feedback ...
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... CPU clock is LOW due to tri-state; both CPUT and CPUC outputs will not be driven. Figure 6. CPU_STP# Deassertion > outputs that were stopped to resume normal operation in a synchronous manner, synchronous manner meaning that no CY28551 Page [+] Feedback ...
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... Figure 8. PCI_STP# Deassertion Tdrive_PCIEX < and 11. The CLKREQ# signal is a debounced signal in that its state must remain unchanged during two consecutive rising edges of DIFC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.) CY28551 Page [+] Feedback ...
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... DIF signals is LOW; both PCIEXT clock and PCIEXC clock outputs will not be driven. Figure 9. CLKREQ# Deassertion Tdrive_PE_R EQ # < Figure 10. VTT_PWRGD# Timing Diagram S1 VTT_PWRGD# = Low Delay > 0. VDD_A = off Normal Operation VTT_PWRGD# = toggle CY28551 S2 Sample Inputs straps Wait for <1.8 ms Enable Outputs Page [+] Feedback ...
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... VTT_PWRGD# PWRGD_VRM 0.2-0.3 ms VDD Clock Gen Clock State State 0 Off Clock Outputs Off Clock VCO Document #: 001-05675 Rev. *C Figure 11. VTT_PWRGD# Timing Diagram Wait for Sample Sels Delay VTT_PWRGD# State 1 State 2 On CY28551 Device is not affected, VTT_PWRGD# is ignored State 3 On Page [+] Feedback ...
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... Condition 3.3 ± 5% SDATA, SCLK SDATA, SCLK Except internal pull-up resistors, 0 < Except internal pull-down resistors, 0 < – max. load and freq. per Figure 14 PD asserted, Outputs Tri-state CY28551 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD –65 150 ° ...
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... Measured at crossing point clock Measured at crossing point clock Measured at crossing point clock Measured at crossing point clock Measured at crossing point clock Measured at crossing point clock CY28551 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10.0 ns – 500 ps – 30 ppm ...
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... Measured at crossing point clock Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured differentially from ±150 mV Measured single-endedly from ±75 mV Math averages, see Figure 14 Math averages, see Figure 14 CY28551 Min. Max. Unit 4.91450 5.11063 ns 3.66463 3.85422 ns 2.91470 3.10038 ns 2 ...
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... Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measured at crossing point V OX Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measured at crossing point V OX Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V CY28551 Min. Max. Unit 300 550 10.4156 10.4177 ns 10.1656 10.6677 ns – 250 ps – ...
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... In High Drive mode Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measured at crossing point V OX Measurement taken from cross point @ 1 µ Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V CY28551 Min. Max. Unit – 250 ps – 500 20.83125 20.83542 ns 20.48125 21.18542 ns 8 ...
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... 2Ω 0Ω Measurement 12Ω Point 50Ω Measurement 12Ω Point 50Ω Measurement 12Ω Point 50Ω Measurement 12Ω Point 50Ω Measurement 12Ω Point 50Ω CY28551 Page [+] Feedback ...
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... L1 = 0.5" 7" 50Ω 22Ω CY28551 M easurem ent Point easurem ent Point ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Package Type CY28551 Product Flow Commercial, 0° to 85°C Commercial, 0° ...
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... C 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0.30[0.012] 0.50[0.020] 0°-12° C SEATING PLANE SIDE VIEW 2 C system, provided that the system conforms to the I CY28551 0.18[0.007] 0.28[0.011] PIN1 ID 0.20[0.008 0.45[0.018] E-PAD (PAD SIZE VARY BY DEVICE TYPE) 0.24[0.009] 0.60[0.024] 0.50[0.020] 7 ...
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... Document History Page Document Title: CY28551 Universal Clock Generator for Intel, VIA, and SIS Document Number: 001-05675 REV. ECN NO. Issue Date ** 409135 See ECN *A 417501 See ECN *B 460105 See ECN *C 491596 See ECN Document #: 001-05675 Rev. *C Orig. of Description of Change Change HGS ...