upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 339

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

A/D
converter
A/D
Converter
Function
When “low-
speed internal
oscillator cannot
be stopped” is
selected by
option byte
when “low-
speed internal
oscillator can be
stopped by
software” is
selected by
option byte
Sampling time
and A/D
conversion time
Block Diagram
ADM: A/D
converter mode
register
ADS: Analog
input channel
specification
register
ADCR: 10-bit
A/D conversion
result register
PMC2: Port
mode control
register 2
A/D converter
operations
Details of
Function
In this mode, operation of the watchdog timer cannot be stopped even during
STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the low-
speed internal oscillation clock can be selected as the count source, so clear the
watchdog timer using the interrupt request of TMH1 before the watchdog timer
overflows after STOP instruction execution. If this processing is not performed,
an internal reset signal is generated when the watchdog timer overflows after
STOP instruction execution.
In this mode, watchdog timer operation is stopped during HALT/STOP instruction
execution. After HALT/STOP mode is released, counting is started again using
the operation clock of the watchdog timer set before HALT/STOP instruction
execution by WDTM. At this time, the counter is not cleared to 0 but holds its
value.
The above sampling time and conversion time do not include the clock frequency
error. Select the sampling time and conversion time such that Notes 2 and 3
above are satisfied, while taking the clock frequency error into consideration (an
error margin maximum of ±5% when using the high-speed internal oscillator).
In the 78K0S/KY1+, V
converter. Be sure to connect V
In the 78K0S/KY1+, V
voltage input. When using the A/D converter, stabilize V
used (2.7 to 5.5 V).
The above sampling time and conversion time do not include the clock frequency
error. Select the conversion time taking the clock frequency error into
consideration (an error margin maximum of ±5% when using the high-speed
internal oscillator).
If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped
(ADCS = 0) and then A/D conversion is started, execute two NOP instructions or
an instruction equivalent to two machine cycles, and set ADCS to 1.
A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2.
Be sure to clear bits 6, 2, and 1 to 0.
Be sure to clear bits 2 to 7 of ADS to 0.
When writing to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined. Read
the conversion result following conversion completion before writing to ADM and
ADS. Using timing other than the above may cause an incorrect conversion result
to be read.
If PMC20 to PMC23 are set to 1, the P20/ANI0/TI000/TOH1,
P21/ANI1/TIO10/TO00/INTP0, P22/ANI2, and P23/ANI3 pins cannot be used for
any purpose other than the A/D converter function..
Make sure the period of <1> to <4> is 1
It is no problem if the order of <1> and <2> is reversed.
<1> can be omitted. However, ignore the data resulting from the first conversion
after <4> in this case.
The period from <5> to <8> differs from the conversion time set using bits 5 to 3
(FR2 to FR0) of ADM. The period from <7> to <8> is the conversion time set
using FR2 to FR0.
APPENDIX C LIST OF CAUTIONS
User’s Manual U16994EJ3V0UD
SS
DD
functions alternately as the ground potential of the A/D
functions alternately as the A/D converter reference
SS
to a stabilized GND (= 0 V).
Cautions
µ
s or more.
DD
at the supply voltage
p. 141
p. 143
p. 148
p. 149
p. 149
p. 153
p. 153
p. 153
p. 153
p. 154
p. 154
p. 155
p. 160
p. 160
p. 160
p. 160
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