sm5302a Nippon Precision Circuits Inc, (NPC), sm5302a Datasheet
sm5302a
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sm5302a Summary of contents
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... OVERVIEW The SM5302A is a 3-channel video buffer with built-in 5th-order lowpass filters. The lowpass filter cutoff fre- quency range can be linearly controlled from 4.8MHz to 43MHz format, video signal equipment analog input/outputs. For video input systems, the device functions as a next- stage ADC system anti-aliasing filter. For video output systems, the filter removes video DAC aliasing and external noise and can drive a maximum of two 75 Ω ...
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... Clamp/Bias/Direct IN1B Clamp/Bias/Direct CH-1 IN2A Clamp/Bias/Direct IN2B Clamp/Bias/Direct CH-2 IN3A Clamp/Bias/Direct IN3B Clamp/Bias/Direct CH-3 Note. The recommended value of the external resistor connected to ISET is 1.8k Ω . SM5302A ADS MUXSEL Current Source Bypass 5th Order LPF MUX Filter (Standard fc) Bypass 5th Order LPF MUX (Standard Filter /Half fc) ...
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... VCC2 − 23 GND1 24 OUT1B O 25 OUT1A O − 26 VCC1 27 REF3 O 28 REF2 O *1. I: input, O: output *2. A: analog, D: digital SM5302A *2 A/D Description A Internal reference voltage 1 D Digital supply (3.0 to 5.5V data signal input/output clock signal input D Digital ground D Input multiplexer switch control 2 ...
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... PIN EQUIVALENT CIRCUITS Number Name I/O 8 IN1A 9 IN1B 11 IN2A I 12 IN2B 13 IN3A 14 IN3B 25 OUT1A 26 OUT1B 21 OUT2A O 20 OUT2B 17 OUT3A 16 OUT3B 1 REF1 O SM5302A Equivalent circuit VCCn INnA INnB GNDn VCCn OUTnA GNDn 750Ω VCCn OUTnB GNDn VCC1 REF1 GND1 SEIKO NPC CORPORATION —4 ...
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... Number Name I/O 28 REF2 O 27 REF3 3 SDA I/O 4 SCL I 6 MUXSEL 7 ADS I Note. Resistance values indicate design values. SM5302A Equivalent circuit VCC1 REF2 GND1 VCC1 REF3 GND1 VDD 250Ω SDA VSS VDD 180Ω SCL MUXSEL VSS VDD 250Ω ADS VSS ...
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... HIGH-level input leakage current I LH SDA output voltage V OL *1. Sum of VCC1 + VCC2 + VCC3 + VDD. No input signals. SM5302A Condition VCC1, VCC2, VCC3, VDD MUXSEL, ADS, SDA, SCL, INnA, INnB ( θ ° C/W Note. θ the measured quantity under the mounted condition which NPC specifi ...
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... SCL setup time (stop condition) t SU;STO SDA, SCL input capacitance *1. This value is not conforming to the I C BUS specification established by Philips Corporation. SDA LOW SCL t t HD;STA HD;DAT S SM5302A Condition min 0 0.6 1.3 0.6 0.6 *1 0.15 100 − − 0.6 − SU;DAT HIGH SU ...
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... Bias mode maximum input AI6 voltage V AI7 V AI8 V IDC1 V IDC2 Direct mode input DC voltage range V IDC3 V IDC4 SM5302A = 1.0Vp- Condition min Clamp input 1.8 Bias input 2.2 − Bias input Mode: b0 (bias, 0dB), THD < 1.0% 1.4 Mode: b6 (bias, 6dB), THD < 1.0% 1.4 Mode: c0 (clamp, 0dB), THD < 1.0% 1.4 Mode: c6 (clamp, 6dB), THD < ...
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... Channel to channel crosstalk X TLK1 MUX input to input crosstalk X TLK2 Drive load resistance response time T IC MUXSEL switch response time T MS SM5302A = 1.0Vp- Condition min − FCDATA = 0 FCDATA = 10 5.98 FCDATA = 227 32.5 − FCDATA = 255 Half fc mode, FCDATA = 10 44 Half fc mode, FCDATA = 227 49 fi ...
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... Bias b6 c0 Clamp c6 d0 Bias d6 e0 Clamp e6 f0 Bias f6 g0 Clamp Direct SM5302A Condition min − REF1 − REF2 − REF3 Output gain CH-3 0dB Bias 6dB 0dB 6dB 0dB 6dB 0dB 6dB 0dB 6dB 0dB 6dB 0dB 6dB ...
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... Input 4.7µ + 4.7µ + 4.7µ ISET Note. This is the electrical characteristics evaluation circuit only, then it is not a recommended application circuit. SM5302A 10µ 10µ REF1 REF2 VDD REF3 SDA VCC1 SCL OUT1A VSS OUT1B GND1 MUXSEL ADS VCC2 IN1A ...
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... Input multiplexer selection 6) Input type switching (sync-tip clamp, bias, direct) 7) Disable function 8) Maximum number of slave addresses It supports fast-mode data transfer rate (up to 400kbit/s). Note that the SM5302A does not have a read function (IC is write only). Basic cycle SDA SCL Start condition The basic access cycle comprises the following elements ...
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... The 3rd byte control data sets the register flags corresponding to the subaddress selected by 2nd byte. The flags assigned are shown in the following table. Register name D7 D6 FCSET FCM FC6 CONDITION1 CB5 CB4 CONDITION2 PD MUX SM5302A 1st byte: slave address ...
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... These flags set the input type of CH-1, CH-2, and CH-3 to one of three types: sync-tip clamp input, bias input, or direct input. Channel CH-1 CH-2 CH-3 *1. An input coupling capacitor should not be connected when direct input is selected. SM5302A 2 + k12 × FCDATA + k13 [MHz k22 × FCDATA + k23 [MHz] Flag name FC6 ...
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... Note that the CH-1 cutoff frequency cannot be switched. This mode is suitable for systems where the sampling frequency varies due to Y, Cr, and Cb requirements, such as digital component signals or digi- tal HDTV signals. Flag name HALF L (CH-1, CH-2, CH-3 cutoff frequency is identical) H (CH-2, CH-3 cutoff frequency is 1/2 that of CH-1) SM5302A Output gain 0dB 6dB Mode Enable (normal operation) Disable (no operation) *1 Input selection ...
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... ADS is Open, that device is subsequently no longer accessible. Flag name Maximum number of slave address NCA 2 L (2-address mode (3-address mode) ADS SM5302A Filter Filter mode Filter bypass mode (signals bypass lowpass filter) Default ADS level LOW HIGH Open LOW HIGH ...
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... SM5302A = 1.8kΩ) ISET FCSET Cutoff freq. FCSET FCDATA (hex) [MHz] (hex) 40 17.19 128 80 41 17.37 129 81 42 17.55 130 82 43 17.73 131 83 44 17.91 132 84 45 18.09 133 85 46 18.27 ...
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... FCDATA Figure 2. Cutoff frequency ratio (half fc mode) * Ratio of CH-2 and CH-3 cutoff frequency at half fc mode based on CH-1 cutoff frequency. SM5302A 128 160 192 224 256 FCDATA 100 Figure 3 ...
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... The REFn pins ( are internal reference voltage outputs µF capacitor connected to ground is recommended for stability. REF1, REF2, and REF3 are independent reference voltage outputs, and have no correspondence with channels CH-1, CH-2, and CH-3. In disable mode, they are high impedance outputs. SM5302A *1 Multiplexer selection ...
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... VSS Slave address = 94h Figure 6. Slave address 94h setting INnA (Used input) Video Signal In INnB (Unused input) Figure 8. Unused analog inputs SM5302A ) and HIGH-level voltage (V ) for each mode is shown > 8cm OUTnA OUTnB Figure 7. Oscillation prevention capacitor connection Video Signal In Figure 9. Direct input mode SEIKO NPC CORPORATION — ...
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... Table 3. Direct mode recommended input DC voltage range (V Mode Gain fc mode setting h0 Standard i0 0dB Half − Standard i6 6dB Half − j6 *1. Refer to figure “Sag Compensation Circuit”. SM5302A = 5V) CC Sag Filter/Bypass compensation Channel mode *1 circuit CH-1 Used CH-2, CH-3 CH-1 Not used CH-2, CH-3 Filter CH-1 Used CH-2, CH-3 ...
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... Figure 12. Gain and Phase characteristics (6dB, standard fc mode, FCDATA = 10) 12 Gain 6 0 Phase -6 -12 -18 -24 -30 -36 -42 -48 0 Frequency [MHz] Figure 14. Gain and Phase Characteristics (6dB, half fc mode, FCDATA = 10) SM5302A = 1.0Vp- 1.8kΩ ISET 270 12 180 -90 -12 -180 -18 -270 -24 -360 -30 ...
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... Figure 16. Gain and Phase characteristics (6dB, standard fc mode, FCDATA = 227) 12 Gain 6 0 Phase -6 -12 -18 -24 -30 -36 -42 -48 0 100 Frequency [MHz] Figure 18. Gain and Phase characteristics (6dB, half fc mode, FCDATA = 227) SM5302A 270 12 Gain 180 -90 -12 -180 -18 -270 -24 -360 -30 -450 -36 Group delay -540 ...
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... Frequency [MHz] Figure 22. Group delay vs. FCDATA, fc mode (6dB) FCDATA (1) 227 (2) 227 (3) 10 (4) 10 SM5302A 0 -90 -180 -270 -360 -450 -540 -630 100 0.1 Figure 21. Phase vs. FCDATA, fc mode (6dB) fc mode standard (1) half (2) standard (3) half ( mode standard ...
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... Ta [°C] Figure 27. Gain vs. Ta (6dB) 1 0.5 0 -0.5 -1 -50 - 100 Ta [°C] Figure 29. Gain vs. Ta (0dB) SM5302A 160 150 140 130 120 110 100 -50 -25 Figure 24. I CC1 *1. filter mode, FCDATA = 255 *2. filter bypass mode 7 6.5 6 5.5 5 256 4 ...
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... Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. SM5302A SEIKO NPC CORPORATION 15-6, Nihombashi-kabutocho, Chuo-ku, ...