sm5903b Seiko NPC Corp., sm5903b Datasheet
sm5903b
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sm5903b Summary of contents
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... NIPPON PRECISION CIRCUITS INC. Overview The SM5903BF is a compression and non com- pression type shock-proof memory controller LSI for compact disc players. The compression level can Features - 2-channel processing - Serial data input ⋅ 2s complement, 16-bit/MSB first, right-justified format ⋅ Wide capture function ( × ...
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... Package dimensions (Unit : mm) 44-pin LQFP Weight : 0.38g 12.80 0.30 10.00 0.30 0.35 0.10 0.80 Pinout (Top View) VDD2 NTEST YSRDATA SM5903BF 0.20 M 0.10 1 UC1 2 UC2 3 UC3 4 UC4 5 UC5 6 N CLK 9 VSS 10 11 (1.40) 0.60 0.20 NWE NCAS 28 27 A10/ NCAS2 YMCLK 26 YMDATA 25 YMLD 24 YDMUTE 23 NIPPON PRECISION CIRCUITS-2 ...
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... Input pin with pull-up resistor Ip/O : Input/Output pin (With pull-up resistor when in input mode) SM5903BF I/O Function - VDD supply pin Ip/O Microcontroller interface extension I/O 1 Ip/O Microcontroller interface extension I/O 2 Ip/O Microcontroller interface extension I/O 3 Ip/O Microcontroller interface extension I/O 4 Ip/O Microcontroller interface extension I ...
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... CLK input frequency f DD1 DD2 SHPRF: Shock-proof, typical values are for DD1 DD2 Note. Refer to pin summary on the next page. SM5903BF (V = 0V, VDD1, VDD2 pin voltage = V SS Rating Unit - 0 125 ˚ ...
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... Pin function Pin name (*3) Pin function Pin name (*4) Pin function Pin name (*5) Pin function Pin name (*6) Pin function Pin name (*7) Pin function Pin name SM5903BF = ˚C) SS Symbol Condition I (*B)SHPRF ON DD (*B)Through mode H level V IH1 L level V IL1 V AC coupling ...
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... Note. When the memory system is OFF (through mode), the input data rate is synchronized to the system clock input (384fs), so input data needs 1/384 of this frequency. But, this IC can tolerate a certain amount of jitter. For details, refer to Through-mode operation. YSCK YSRDATA YLRCK SM5903BF = - ˚ - ˚C SS Symbol ...
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... Reset input (NRESET pin) Parameter First HIGH-level after supply voltage rising edge NRESET pulsewidth t Note. is the system clock (CLK) input (384fs) cycle time (min) = 3.8 µs when fs = 44.1 kHz = 59 ns, CY NRST VDD1,VDD2 NRESET SM5903BF Symbol Min MCWL MCWH ...
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... Input hold NWE pulsewidth NWE falling edge to NCAS falling edge Refresh cycle (fs = 44.1 kHz playback) Memory system ON Decode sequence operation (RDEN=H) t Note. is the system clock (CLK) input (384fs) cycle time. CY SM5903BF Symbol Condition Min load SCOW load SCOY load ...
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... (WRITE (READ) NWE (WRITE) t WCS The NWE terminal output is fixed HIGH during read timing. NCAS terminal output is fixed HIGH when selecting "DRAM2". NCAS2 terminal output is fixed HIGH when selecting "DRAM1". SM5903BF t RASL RCD CASL ...
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... Block diagram SM5903 YBLKCK Control YFCLK Input 1 YFLAG YMDATA YMCLK Micro- controller Interface YMLD ZSENSE General UC1 to UC5 Port YDMUTE Control NRESET Input 2 NTEST SM5903BF Output Interface Compression Through Mode Mode Decoder DRAM Interface NIPPON PRECISION CIRCUITS-10 Input Interface Input Buffer Encoder ...
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... Functional description SM5903BF has two modes of operation; shock- proof mode and through mode. Microcontroller interface Command format Commands from the microcontroller are input using 3-wire serial interface inputs; data (YMDATA), bit clock (YMCLK) and load signal (YMLD). Write command format (Commands 80 to 85) ...
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... UC5WD D3 UC4WD D2 UC3WD D1 UC2WD D0 UC1WD SM5903BF Function Encode sequence start/stop Write address reset Decode sequence start/stop Read address reset Q data valid Memory system ON Function Extension I/O port UC5 input/output setting Extension I/O port UC4 input/output setting Extension I/O port UC3 input/output setting Extension I/O port UC2 input/output setting ...
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... COMP6B D1 COMP5B D0 COMP4B When the number of compression bits is set incorrectly (2 or more bits are set all bits are set to 0), SM5903BF Function Forced muting (changes instantaneously) Refer to "Force mute", "12-bit comparison connection". Function DRAM type setting - When YFLGS=1, YFCKP=0, YFLAG=L ...
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... Write overflow state (Always HIGH when WA exceeds RA) S5 ENCOD Encode sequence operating state S4 DECOD Decode sequence operating state SM5903BF Function Function NIPPON PRECISION CIRCUITS-14 90hex = 1001 0000 HIGH-level state Exceeded DRAM overflow Input buffer memory overflow Compare-connect sequence operating ...
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... OR the output data from a pin configured as an output port using the 82H command.) Bit Name UC5RD S3 UC4RD S2 UC3RD S1 UC2RD S0 UC1RD SM5903BF Function 4M bits 2M bits 1M bits 512k bits 256k bits 128k bits 64k bits 32k bits 16k bits 8k bits 4k bits 2k bits 1k bits 512 bits 256 bits Residual time (sec) = Valid data residual (Mbits) × ...
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... Set Reset - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued SM5903BF disturbance has exceeded the RAM jitter margin. - Set according to the YFLAG input and the operating state of YFCKP and YFLGS. FLAG6 set conditions When YFLGS=0, YFCKP=0, YFCLK input falling edge, YFLAG=L ...
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... Meaning 91H bit 4 Set Reset SM5903BF - Indicates that the valid data residual has become 0 - When the VWA (final valid data's next address (address from which the next read would take place) - Whenever the above does not apply - Indicates a write to external DRAM overflow state - When the write address (WA) exceeds the read address (RA) ...
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... MSRDEN flag setting is maintained as is, the sequence automatically re-starts when valid data appears. When 0: Decode sequence stops 81H (Extension I/O port settings) 82H (Extension I/O port output data settings) SM5903BF -MSRACL When 1: Initializes the read address (RA) When 0: No operation - MSDCN2, MSDCN1 When 1 and 1: 3-pair compare-connect sequence ...
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... When 0 and 1: Sets FLAG6 on the rising edge of YFCLK when YFLAG=0 When 1 and 0: Sets FLAG6 when YFLAG=0 When 1 and 1: Sets FLAG6 when YFLAG=1 SM5903BF - MUTE, YDMUTE relationship When all mute inputs are 0, mute is released. - CMP12 (12-bit comparison connection) When 1: Performs comparison connection using only the most significant 12 bits of input data ...
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... Then, using microcontroller command 80H, the compare-connect start command is executed and compare-connect sequence starts. SM5903BF troller command 80H. This mode comprises the following 3 sequences. 3. The encoder, after the most suitable predicting filter type and quantization steps have been deter- mined, performs ADPCM encoding and then writes to external DRAM ...
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... RAM addresses The SM5903BF uses either external DRAMs as external buffers. Three kinds of addresses are used for external RAM control. WA (write address) RA (read address) VWA (valid write address) Among these, VWA is the write address for con- forming data whose validity has been confirmed. ...
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... When YFLAG=LOW 4 1 When YFLAG=HIGH SM5903BF encode sequence when such a disturbance has occurred, and then makes FLAG6 active. The YFLAG check method used changes depend- ing on the YFLGS flag and YFCKP flag (85H com- mand). See table1. If YFLAGS is set to 1, then YFCLK should be tied either High or Low ...
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... The SM5903BF supports three kinds of connect modes; 3-pair compare-connect, 2-pair compare- connect and direct connect. Note that the SM5903BF can also operate in 12-bit comparison connect mode using only the most sig- nificant 12 bits of data for connection operation. In 3-pair compare-connect mode, the final 6 valid ...
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... Data compression mode 1M (256K×4 bits) 4 bit 5 bit 6 bit Full bit SM5903BF - But if the MSWREN is set HIGH (80H command) after using the compare-connect start command even only once, data is written to VWA. If data is input before comparison and conformance is detected, the same operation as direct-connect mode takes place when the command is issued ...
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... When the CMP12 flag is set to 1, the least signifi- cant 4 bits of the 16-bit comparison connection input data are discarded and comparison connec- tion is performed using the remaining 12 bits. SM5903BF clock be at rate fs by the time jitter-free timing starts. The jitter margin is 0.2/ fs (80 clock cycles). ...
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... Timing charts Input timing (YSCK, YSRDATA, YLRCK) YSCK YSRDATA YLRCK Output timing (ZSCK, ZSRDATA, ZLRCK ZSCK ZSRDATA ZLRCK SM5903BF 1/(3fs ) 1/ NIPPON PRECISION CIRCUITS-26 ...
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... Write timing (with single DRAM) NRAS NCAS t RADS A0 to A10 (WRITE) NWE Write timing (with double DRAMs) NRAS NCAS1 (DRAM1 SELECT) NCAS2 (DRAM2 SELECT) t RADS (WRITE) NWE SM5903BF t RASL t t RDC CASL RADH CADS CADH t t CWDS CWDH t WEL t RASL ...
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... Read timing (with single DRAM) NRAS NCAS t RADS A0 to A10 (READ) NWE Read timing (with double DRAMs) NRAS NCAS1 (DRAM1 SELECT) NCAS2 (DRAM2 SELECT) t RADS (READ) NWE SM5903BF t RASL t t RCD CASL RADH CADS CADH t CRDS t OEL t RASL t t ...
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... When double DRAMs are used, the DRAM OE pins should be tied LOW. - When single DRAM is used, the DRAM OE pin should be tied LOW or controlled by the SM5903BF NOE signal. note 2 When CXD 2517 (Sony) is used Set 85H of microcontroller command (option setting) as setting YFLAG take in; ...
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... D0 to D11 91H S3 Compression mode switching Compression mode switching using 85 H command of SM5903BF can’t be changed during shockproof operation. In order to switch compression mode necessary to change it to “through-mode” first Attentions About SM5903BF, Soft mute function and Attenuation function are deleted. In order not to ...
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... Customers shall not export, directly or indirect- ly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. SM5903BF reserves the right to make changes to the products described in this data sheet in order to NIPPON PRECISION CIRCUITS INC. ...