SST25VF512 Silicon Storage Technology, Inc., SST25VF512 Datasheet - Page 7

• Manufacturer Part Number: SST25VF512
• Description: 512 Kbit Spi Serial Flash
• Manufacturer: Silicon Storage Technology, Inc.

512 Kbit SPI Serial Flash
SST25VF512
Auto Address Increment (AAI)
The Auto Address Increment Programming-Status bit pro-
vides status on whether the device is in AAI programming
mode or Byte-Program mode. The default at power up is
Byte-Program mode.
Instructions
Instructions are used to Read, Write (Erase and Program),
and configure the SST25VF512. The instruction bus cycles
are 8 bits each for commands (Op Code), data, and
addresses. Prior to executing any Byte-Program, Auto
Address Increment (AAI) programming, Sector-Erase,
Block-Erase, or Chip-Erase instructions, the Write-Enable
TABLE 6: D
©2005 Silicon Storage Technology, Inc.
Bus Cycle
Cycle Type/Operation
Read
Sector-Erase
Block-Erase
Chip-Erase
Byte-Program
Auto Address Increment (AAI) Program
Read-Status-Register (RDSR)
Enable-Write-Status-Register (EWSR)
Write-Status-Register (WRSR)
Write-Enable (WREN)
Write-Disable (WRDI)
Read-ID
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of
11. Manufacturer’s ID is read with A
12. Device ID = 48H for SST25VF512
1. A
2. One bus cycle is eight clock periods.
3. Operation: S
4. X = Dummy Input Cycles (V
5. Sector addresses: use A
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable (WREN) instruction
7. Block addresses for: use A
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
A
Address bits above the most significant bit of each density can be V
must be executed.
followed by the data to be programmed.
each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
ID output stream is continuous until terminated by a low to high transition on CE#
MS
MS
= A
= Most Significant Address
2
6
5,7
15
5,6
6
for SST25VF512
EVICE
IN
= Serial In, S
O
3,4
PERATION
MS
MS
-A
IL
OUT
10
12
-A
or V
, remaining addresses can be V
15
0
= Serial Out
=0, and Device ID is read with A
, remaining addresses can be V
I
IH
NSTRUCTIONS
); - = Non-Applicable Cycles (Cycles are not necessary)
10
6,8
90H or
AFH
ABH
03H
20H
52H
60H
02H
05H
50H
01H
06H
04H
S
IN
1
1
S
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
A
A
A
A
A
Data
IL
23
23
23
23
23
00H
7
S
0
X
or V
IL
-A
-A
-A
-
-A
-A
-
-
-
IN
=1. All other address bits are 00H. The Manufacturer’s and Device
or V
IL
(WREN) instruction must be executed first. The complete
list of the instructions is provided in Table 6. All instructions
are synchronized off a high to low transition of CE#. Inputs
will be accepted on the rising edge of SCK starting with the
most significant bit. CE# must be driven low before an
instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low
to high transition on CE#, before receiving the last bit of an
instruction bus cycle, will terminate the instruction in
progress and return the device to the standby mode.
Instruction commands (Op Code), addresses, and data are
all input from the most significant bit (MSB) first.
16
16
16
16
16
2
IH
or V
IH
D
S
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IH
OUT
OUT
-
-
-
-
A
A
A
A
A
00H
15
15
15
15
15
S
-
-
-
-
-
-
IN
-A
-A
-A
-A
-A
8
8
8
8
8
3
Note
S
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
-
-
-
-
-
9
ID Addr
A
A
A
A
A
S
7
7
7
7
7
-.
-A
-A
-A
-
-A
-A
-
-
-
-
IN
0
0
0
0
0
11
4
Note
S
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
S71192-08-000
-
-
-
-
-
9
S
D
D
Data Sheet
X
X
-
-
-
-
-
-
-
-
IN
IN
IN
D
5
T6.18 1192
Note
D
S
Hi-Z
Hi-Z
OUT
OUT
OUT
-
-
-
-
-
-
-
11/05
12
9