SST25VF010 Silicon Storage Technology, Inc., SST25VF010 Datasheet
SST25VF010
Available stocks
Related parts for SST25VF010
SST25VF010 Summary of contents
Page 1
... The SST25VF010 device operates with a single 2.7-3.6V power supply. with alternate The SST25VF010 device is offered in both 8-lead SOIC and 8-contact WSON packages. See Figure 1 for the pin assignments. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Data Sheet ...
Page 2
... Data Sheet UNCTIONAL LOCK IAGRAM Address Buffers and Latches CE# ©2006 Silicon Storage Technology, Inc Decoder Control Logic Serial Interface SCK SI SO WP# HOLD Mbit SPI Serial Flash SST25VF010 SuperFlash Memory Y - Decoder I/O Buffers and Data Latches 1233 B1.0 S71233-05-000 1/06 ...
Page 3
... Mbit SPI Serial Flash SST25VF010 PIN DESCRIPTION CE Top View WP 1233 08-soic P1.0 8- SOIC LEAD FIGURE SSIGNMENTS TABLE ESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input ...
Page 4
... BFH Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). 49H The SST25VF010 supports both Mode 0 (0,0) and Mode 3 T2.0 1233 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 2, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
Page 5
... W OLD ONDITION Write Protection The SST25VF010 provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 4 for Block-Protection description ...
Page 6
... The Auto Address Increment Programming-Status bit pro- vides status on whether the device is in AAI programming mode or Byte-Program mode. The default at power up is Byte-Program mode. Default at Power- SST25VF010 R EGISTER 1 Protected Memory Area None 018000H-01FFFFH 010000H-01FFFFH 000000H-01FFFFH T4.0 1233 Read/Write R ...
Page 7
... Mbit SPI Serial Flash SST25VF010 Instructions Instructions are used to Read, Write (Erase and Program), and configure the SST25VF010. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first ...
Page 8
... The user may poll the Busy bit in the software status register or wait T self-timed Byte-Program operation. See Figure 5 for the Byte-Program sequence ADD. ADD. MSB MSB HIGH IMPEDANCE 8 1 Mbit SPI Serial Flash SST25VF010 -A ]. CE# must N+1 N+2 N+3 N ...
Page 9
... Mbit SPI Serial Flash SST25VF010 Auto Address Increment (AAI) Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total program- ming time when the entire memory array pro- grammed ...
Page 10
... Erase cycle. See Figure 8 for the Block-Erase sequence ADD. ADD. MSB MSB HIGH IMPEDANCE 10 1 Mbit SPI Serial Flash SST25VF010 ), remaining address bits can for the completion of the internal self ADD. 1233 F07.1 ]. Address bits [ Most ...
Page 11
... Mbit SPI Serial Flash SST25VF010 Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence ...
Page 12
... MODE 0 SCK 04 SI MSB HIGH IMPEDANCE SO 1233 F12.1 EQUENCE Status-Register (WRSR) instruction. CE# must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed Mbit SPI Serial Flash SST25VF010 S71233-05-000 1/06 ...
Page 13
... Mbit SPI Serial Flash SST25VF010 Write-Status-Register (WRSR) The Write-Status-Register instruction works in conjunction with the Enable-Write-Status-Register (EWSR) instruction to write new values to the BP1, BP0, and BPL bits of the status register. The Write-Status-Register instruction must be executed immediately after the execution of the Enable- Write-Status-Register instruction (very next instruction bus cycle) ...
Page 14
... Data Sheet Read-ID The Read-ID instruction identifies the device as SST25VF010 and manufacturer as SST. The device infor- mation can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A Read-ID instruction, the manufacturer’ located in CE# MODE ...
Page 15
... Mbit SPI Serial Flash SST25VF010 ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55° ...
Page 16
... Years 100 + 2.7-3.6V DD Min 100 Mbit SPI Serial Flash SST25VF010 Test Method JEDEC Standard A117 JEDEC Standard A103 mA JEDEC Standard 78 T10.0 1233 Limits Max Units 20 MHz ...
Page 17
... Mbit SPI Serial Flash SST25VF010 CE# T CHH T CES SCK MSB SI SO HIGH-Z FIGURE 15 ERIAL NPUT IMING CE# T SCKH SCK T CLZ SO SI FIGURE 16 ERIAL UTPUT IMING ©2006 Silicon Storage Technology, Inc. T SCKF T SCKR D IAGRAM T SCKL T OH ...
Page 18
... All commands are rejected by the device. V Min DD FIGURE 18 OWER UP IMING ©2006 Silicon Storage Technology, Inc HHH HLS T HLH PU-READ T PU-WRITE D IAGRAM 18 1 Mbit SPI Serial Flash SST25VF010 T HHS T LZ Device fully accessible Time 1233 F18.0 S71233-05-000 1233 F17.0 1/06 ...
Page 19
... Mbit SPI Serial Flash SST25VF010 V IHT INPUT V ILT AC test inputs are driven at V (0.9V IHT for inputs and outputs are V (0.7V HT FIGURE 19 NPUT UTPUT FIGURE 20 EST OAD XAMPLE ©2006 Silicon Storage Technology, Inc REFERENCE POINTS for a logic “1” and V (0 ...
Page 20
... Suffix1 SST25VFxxx - XXX - XX Valid combinations for SST25VF010 SST25VF010-20-4C-SAE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2006 Silicon Storage Technology, Inc. Suffix2 ...
Page 21
... Mbit SPI Serial Flash SST25VF010 PACKAGING DIAGRAMS Pin #1 Identifier TOP VIEW 5.0 4.8 4.00 3.80 6.20 5.80 Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends and 0.25 mm between leads. ...
Page 22
... Max 0.80 0.70 leads. 1mm SS of the unit (WSON) UTLINE O LEAD Description www.SuperFlash.com or www.sst.com 22 1 Mbit SPI Serial Flash SST25VF010 BOTTOM VIEW Pin #1 1.27 BSC 4.0 0.48 0.35 3.4 0.70 0.50 CROSS SECTION 0.80 0.70 8-wson-5x6-QA-9.0 Date Apr 2003 Aug 2003 Dec 2003 Feb 2004 Jan 2005 Jan 2006 ...