S25FL128K Meet Spansion Inc., S25FL128K Datasheet - Page 25

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S25FL128K

Manufacturer Part Number
S25FL128K
Description
128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
Manufacturer
Meet Spansion Inc.
Datasheet
April 1, 2011 S25FL128K_00_02
6.2.9
Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except
that data is output on four pins, IO0, IO1, IO2, and IO3. A Quad enable of Status Register-2 must be executed
before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1).
The Fast Read Quad Output Instruction allows data to be transferred from the S25FL128K at four times the
rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of F
Electrical Characteristics on page
address as shown in
setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins
should be high-impedance prior to the falling edge of the first data out clock.
CLK
CS
IO3
IO1
CLK
IO0
IO2
CS
D a t a
IO1
IO3
IO0
IO2
Mode 3
Mode 0
Figure 6.11 Fast Read Quad Output Instruction Sequence Diagram
Figure
S h e e t
32
0
6.11. The dummy clocks allow the device's internal circuits additional time for
33
1
34
Dummy Clocks
54.). This is accomplished by adding eight “dummy” clocks after the 24-bit
( P r e l i m i n a r y )
2
Instruction (6Bh)
35
3
S25FL128K
36
4
37
5
38
6
39
7
40
4
5
7
6
Byte 1 Byte 2
23
8
0
1
3
2
41
22
IO_0 Switches from Input to Output
9
4
5
7
6
42
21
24-Bit Address
10
0
1
3
2
43
4
5
6
Byte 3
7
44
3
28
1
2
0
3
2
45
29
4
5
6
Byte 4
1
7
46 47
30 31
0
1
3
2
0
4
5
7
6
R
(See AC
25

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