S25FL128K Meet Spansion Inc., S25FL128K Datasheet - Page 37

• Manufacturer Part Number: S25FL128K
• Description: 128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

April 1, 2011 S25FL128K_00_02
6.2.21
6.2.22
64 KB Block Erase (D8h)
Chip Erase (C7h / 60h)
The Block Erase instruction sets all memory within a specified block (64 kbytes) to the erased state of all 1s
(FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the
instruction code “D8h” followed a 24-bit block address (A23-A0)
Erase instruction sequence is shown in
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After CS# is driven high, the self-timed Block Erase instruction
will commence for a time duration of t
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished
and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed
if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits. See
Table 6.2, Status Register Memory Protection (CMP = 0) on page
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register
bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the instruction code
“C7h” or “60h”. The Chip Erase instruction sequence is shown in
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After CS# is driven high, the self-timed Chip Erase instruction will commence
CLK
CS#
SO
SI
D a t a
= MSB
Mode 3
Mode 0
CLK
SIO
CS#
SO
S h e e t
Mode 3
Figure 6.25 32 kB Block Erase Instruction Sequence Diagram
Figure 6.26 64 kB Block Erase Instruction Sequence Diagram
Mode 0
= MSB
0
1
0
( P r e l i m i n a r y )
1
2
Instruction (D8h)
BE
Instruction (52h)
2
S25FL128K
Figure
(see
3
3
See AC Electrical Characteristics on page
4
4
6.26.
High Impedance
5
5
High Impedance
6
6
7
7
23 22
8
23
8
9
24-Bit Address
See Block Diagram on page 8.
22
Figure
15.
9
24-Bit Address
2
29 30 31
6.27.
1
2
29
0
1
Mode 3
Mode 0
30
0
31
54.). While the Block
Mode 3
Mode 0
The Block
37