S25FL128P Meet Spansion Inc., S25FL128P Datasheet - Page 12

• Manufacturer Part Number: S25FL128P
• Description: 128 Megabit Cmos 3.0 Volt Flash Memory With 104 Mhz Spi Serial Peripheral Interface Bus
• Manufacturer: Meet Spansion Inc.

7. Device Operations
7.1
7.2
7.3
7.4
7.5
7.6
12
Byte or Page Programming
Sector Erase / Bulk Erase
Monitoring Write Operations Using the Status Register
Active Power and Standby Power Modes
Status Register
Data Protection Modes
All Spansion SPI devices (S25FL-P) accept and output data in bytes (8 bits at a time).
Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program
(PP) sequence, which consists of four bytes plus data. The Page Program sequence accepts from 1 byte up
to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation.
Programming means that bits can either be left at 0, or programmed from 1 to 0. Changing bits from 0 to 1
requires an erase operation. Before this can be applied, the bytes of the memory need to be first erased to all
1’s (FFh) before any programming.
The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array
to 1. While bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a
sector-wide (SE) or array-wide (BE) level. Before this can be applied, the memory array need to be first
erased to all 1's (FFh) before any programming.
The host system can determine when a Write Status Register, program, or erase operation is complete by
monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register command
provides the state of the WIP bit.
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the
device is disabled, but may still be in the Active Power mode until all program, erase, and Write Status
Register operations have completed. The device then goes into the Standby Power mode, and power
consumption drops to I
inadvertent signals. After writing the DP command, the device ignores any further program or erase
commands, and reduces its power consumption to I
The Status Register contains the status and control bits that can be read or set by specific commands (see
Table
Spansion SPI Flash memory devices provide the following data protection methods:
Write In Progress (WIP): Indicates whether the device is performing a Write Status Register, program or
erase operation.
Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch.
Block Protect (BP2, BP1, BP0 for uniform 256 KB sector product: BP3, BP2, BP1, BP0 for uniform
64 KB sector product): Non-volatile bits that define memory area to be software-protected against
program and erase commands.
Status Register Write Disable (SRWD): Places the device in the Hardware Protected mode when this bit
is set to 1 and the WP#/ACC input is driven low. In this mode, the non-volatile bits of the Status Register
(SRWD, BP3, BP2, BP1, BP0) become read-only bits.
The Write Enable (WREN) command: Must be written prior to any command that modifies data. The
WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up
or after the device completes the following commands:
– Page Program (PP)
Table 11.6, Command Definitions on page
SB
. The Deep Power Down (DP) command provides additional data protection against
D a t a
S25FL128P
S h e e t
38):
DP
( P r e l i m i n a r y )
.
S25FL128P_00_04 July 2, 2007