S25FL128P Meet Spansion Inc., S25FL128P Datasheet - Page 29

• Manufacturer Part Number: S25FL128P
• Description: 128 Megabit Cmos 3.0 Volt Flash Memory With 104 Mhz Spi Serial Peripheral Interface Bus
• Manufacturer: Meet Spansion Inc.

11.8
July 2, 2007 S25FL128P_00_04
Write Status Register (WRSR: 01h)
The Write Status Register (WRSR) command changes the bits in the Status Register. A Write Enable
(WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is required prior to
writing the WRSR command.
shows the status register bits and their functions.
The host system must drive CS# low, write the WRSR command, and the appropriate data byte on SI
(Figure
The WRSR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must
be used for that purpose. Bit 0 is a status bit controlled internally by the Flash device. Bits 6 and 5 are always
read as 0 and have no user significance.
The WRSR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit
and WP#/ACC together place the device in the Hardware Protected Mode (HPM). The device ignores all
WRSR commands once it enters the Hardware Protected Mode (HPM).
must be driven low and the SRWD bit must be 1 for this to occur.
Notes
1. Instruction byte = 01h
2. In parallel mode, the maximum access clock frequency (Fsck) is 10 MHz (SCK pin clock frequency).
3. Writing to the Status Register in parallel mode requires a Parallel Mode Entry command (55h) to be issued before the RDSR command.
Once in the parallel mode, the flash memory will not exit the parallel mode until a Parallel Mode Exit (45h) command is given to the flash
device, or upon power-down or power-up sequence.
11.12).
D a t a
Figure 11.13 Parallel Write Status Register (WRSR) Command Sequence
Figure 11.12 Write Status Register (WRSR) Command Sequence
S h e e t
PO[7-0]
SCK
CS#
CS#
SCK
SI
SO
SI
Table 11.3, S25FL128P Status Register (Uniform 256 KB sector) on page 26
Mode 3
Mode 0
Hi-Z
Mode 3
Mode 0
Hi-Z
( P r e l i m i n a r y )
0
S25FL128P
0
1
1
2
Command
2
Command
3
3
4
4
5
5
6
6
7
MSB
7
Byte 1
7
8 9 10 11 12 13 14 15
8 9 10 11 12 13 14 15
6
Status Register In
5
Status Register In
4
3
2
Table 11.5
1
0
shows that WP#/ACC
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