cs4239 Cirrus Logic, Inc., cs4239 Datasheet - Page 33

• Manufacturer Part Number: cs4239
• Description: Crystalclear? Ortable Isa Audio System Logic
• Manufacturer: Cirrus Logic, Inc.

CD7-CD0
The reading of this register will increment the
state machine so that the following read will be
from the next appropriate byte in the sample.
The exact byte which is next to be read can be
determined by reading the Status register (R2).
Once all relevant bytes have been read, the state
machine will point to the last byte of the sample
until a new sample is received from the ADCs.
Once the Status register (R2) is read and a new
sample is received from the FIFO, the state ma-
chine and Status register (R2) will point to the
first byte of the new sample.
During initialization and software power down
of the WSS Codec, this register can NOT be
written and is always read 10000000 (80h)
PD7-PD0
Writing data to this register will increment the
playback byte tracking state machine so that the
following write will be to the correct byte of the
sample. Once all bytes of a sample have been
written, subsequent byte writes to this port are
ignored. The state machine is reset after the
Status register (R2) is read, and the current sam-
ple is sent to the DACs via the FIFOs.
DS253PP2
Capture I/O Data Register
(WSSbase+3, R3, Read Only)
Playback I/O Data Register
WSSbase+3, R3, Write Only)
CD7
PD7
D7
D7
CD6
PD6
D6
D6
CD5
PD5
D5
D5
Capture Data Port. This is the control
register where capture data is read
during programmed I/O data trans-
fers.
Playback Data Port. This is the
control register where playback data
is written during programmed IO
data transfers.
CD4
PD4
D4
D4
CD3
PD3
D3
D3
CD2
PD2
D2
D2
CD1
PD1
D1
D1
CD0
PD0
D0
D0
INDIRECT MAPPED REGISTERS
These registers are accessed by placing the ap-
propriate index in the Index Address register
(R0) and then accessing the Indexed Data regis-
ter (R1). A detailed description of each indirect
register is given below. All reserved bits should
be written zero and may be 0 or 1 when read.
Note that indirect registers 16-31 are not avail-
able when in MODE 1 (CMS1,0 in MODE and
ID register I12 are both zero).
Left Analog Loopback (I0)
Default = 000xxxxx
MGE
LSS1-LSS0
Right Analog Loopback(I1)
Default = 000xxxxx
MGE
RSS1-RSS0
RSS1
LSS1
D7
D7
LSS0
RSS0
D6
D6
CrystalClear Portable ISA Audio System
MGE
D5
MGE
D5
This bit controls the 20 dB gain boost
for the MIC analog input.
bits to 11 enables the left output
loopback into the input mixer. Bit
combinations of 01, 10, and 00 dis-
able the loopback.
This bit is identical to the MGE bit in
I0. It controls the 20 dB gain boost
for the MIC analog input.
bits to 11 enables the right output
loopback into the input mixer. Other
bit combinations disable the loop-
back.
Left output loopback. Setting these
Right output loopback. Setting these
D4
res
D4
res
TM
D3
rbc
D3
rbc
D2
rbc
D2
rbc
D1
rbc
D1
rbc
CS4239
D0
rbc
D0
rbc
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