cs4237b Cirrus Logic, Inc., cs4237b Datasheet - Page 25

• Manufacturer Part Number: cs4237b
• Description: Crystalclear Advanced Audio System With 3d Sound
• Manufacturer: Cirrus Logic, Inc.

The E
2-wire interface consisting of a bi-directional
data line and a clock line driven from the part.
After power-on the part looks for the existence
of an E
fined data. The existence is determined by the
first two bytes read (0x55 followed by 0xBB). If
the first two bytes are correct, the part reads the
next two bytes to determine the length of data in
the E
number of bytes left to be read (not including
the two validation bytes or two length bytes). As
shown in Figure 3, the E
start bit followed by a dummy write, to initialize
the address to zero. Then another start bit and
device address, followed by all the data. Since
the part uses the sequential read properties of the
E
(ganged E
Some E
interface are:
where the xx is replaced by 02, 04, 08, or 16
based on the size of the E
size of 16 (2k bytes) is preferred since it allows
the maximum flexibility for upgrading firmware
patches. Other E
ure 3 and the timing parameters listed in the
front of the data sheet may also be used.
DS213PP4
2
Crystal IC
EEPROM
PROM, only one E
Atmel
MicroChip
National
Ramtron
SGS Thompson
Xicor
2
2
PROM interface uses an industry standard
PROM. The length bytes indicate the
2
2
PROM device and loads the user de-
PROMs that are compatible with this
2
PROMs are not supported).
Start
S 1 0 1 0 0 0 0 0 A 0 0 0 0 0 0 0 0 A S 1 0 1 0 0 0 0 1 A
2
PROMs compatible with Fig-
Address
Part
AT24Cxx series
24LCxxB series
NM24CxxL series
FM24Cxx series
ST24Cxx series
X24Cxx series
2
2
PROM is read using a
PROM, is supported
2
Write
PROM desired. The
Address
Bank
Figure 3. EEPROM Format
Acknowledge
Start
Address
Part
The maximum Hardware Configuration and PnP
resource RAM data supported is 384 bytes, and
a four byte header; therefore, the maximum
amount of data storage, without firmware
patches, in E
maximum size E
This allows the inclusion of firmware patches af-
ter the PnP resource data.
If an external E
the serial interface and is connected to the XD0
and XA0 pins. The two-wire interface is control-
led by three bits in the Control logical device,
Hardware Control Register (CTRLbase+1). The
serial data can be written to or read from the
E
register. The three register bits, D0, D1, D2 are
labeled CLK, DOUT, and DIN/EEN respectively.
The DIN/EEN bit, when written to a one, en-
ables the E
DIN/EEN bit is written to a zero, the serial inter-
face is disabled. The DIN/EEN bit is also the
Data In (DIN) signal to read back data from the
E
drain data line supporting DIN and DOUT;
therefore, to read the correct data, the DOUT bit
must be set to a one prior to performing a read
of the register. Otherwise, the data read back
from DIN/EEN will be all zeros. The E
data can then be read from the DIN/EEN bit.
The CLK bit timing is controlled by the host
software. This is the serial clock for the
E
gram the data out to the E
pull-up resistor is required on XD0 because it is
an open-drain output. Use the guidelines in the
2
2
2
PROM by sequentially writing or reading that
PROM. The XD0 pin is a bi-directional open-
PROM. The DOUT bit is used to write/pro-
Read
2
PROM serial interface. When the
2
PROM would be 388 bytes. The
Data
2
Acknowledge
PROM exists, it is accessed by
2
PROM supported is 2k bytes.
Data
A
2
PROM. An external
Data
Acknowledge
No
CS4237B
1
P
2
PROM
Stop
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