st62t62c STMicroelectronics, st62t62c Datasheet - Page 56

• Manufacturer Part Number: st62t62c
• Description: 8-bit Otp/eprom Mcus With A/d Converter, Safe Reset, Auto-reload Timer And Eeprom
• Manufacturer: STMicroelectronics

Abbreviations for Addressing Modes: Legend:
dir
sd
imm
inh
ext
b.d
bt
pcr
ind
ST62T52C ST62T62C/E62C
Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
56/78
HI
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
Direct
Short Direct
Immediate
Inherent
Extended
Bit Direct
Bit Test
Program Counter Relative
Indirect
LOW
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
0000
RNZ
0
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
JRNZ 4
JRNZ 4
JRNZ 4
JRNZ 4
JRNZ 4
JRNZ 4
JRNZ 4
JRNZ 4
JRNZ 4
JRNZ 4
JRNZ 4
JRNZ 4
JRNZ 4
JRNZ 4
JRNZ 4
pcr 2
pcr 2
pcr 2
pcr 2
pcr 2
pcr 2
pcr 2
pcr 2
pcr 2
pcr 2
pcr 2
pcr 2
pcr 2
pcr 2
pcr 2
pcr 2
4
0001
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
1
CALL 2
CALL 2
CALL 2
CALL 2
CALL 2
CALL 2
CALL 2
CALL 2
CALL 2
CALL 2
CALL 2
CALL 2
CALL 2
CALL 2
CALL 2
CALL 2
ext 1
ext 1
ext 1
ext 1
ext 1
ext 1
ext 1
ext 1
ext 1
ext 1
ext 1
ext 1
ext 1
ext 1
ext 1
ext 1
b
rr
nn
abc
ee
#
e
0010
2
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
3 Bit Address
1 byte immediate data
12 bit address
8 bit Displacement
Indicates Illegal Instructions
5 Bit Displacement
1byte dataspace address
JRNC 5
JRNC 5
JRNC 5
JRNC 5
JRNC 5
JRNC 5
JRNC 5
JRNC 5
JRNC 5
JRNC 5
JRNC 5
JRNC 5
JRNC 5
JRNC 5
JRNC 5
JRNC 5
pcr 3
pcr 3
pcr 3
pcr 3
pcr 3
pcr 3
pcr 3
pcr 3
pcr 3
pcr 3
pcr 3
pcr 3
pcr 3
pcr 3
pcr 3
pcr 3
b4,rr,ee
b2,rr,ee
b6,rr,ee
b6,rr,ee
b1,rr,ee
b1,rr,ee
b5,rr,ee
b5,rr,ee
b3,rr,ee
b3,rr,ee
b7,rr,ee
b7,rr,ee
b0,rr,ee
b0,rr,ee
b4,rr,ee
b2,rr,ee
0011
3
JRR 2
JRR 2
JRR 2
JRR 2
JRR 2
JRR 2
JRR 2
JRR 2
JRS 2
JRS 2
JRS 2
JRS 2
JRS 2
JRS 2
JRS 2
JRS 2
bt 1
bt 1
bt 1
bt 1
bt 1
bt 1
bt 1
bt 1
bt 1
bt 1
bt 1
bt 1
bt 1
bt 1
bt 1
bt 1
e
0100
4
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
JRZ
JRZ 4
JRZ
JRZ 4
JRZ
JRZ 4
JRZ
JRZ 4
JRZ
JRZ 4
JRZ
JRZ 4
JRZ
JRZ 4
JRZ
JRZ 4
pcr
pcr 1
pcr
pcr 1
pcr
pcr 1
pcr
pcr 1
pcr
pcr 1
pcr
pcr 1
pcr
pcr 1
pcr
pcr 1
Cycle
Operand
Bytes
Addressing Mode
0101
a,w
a,x
a,v
a,y
w
5
#
x
#
#
y
#
#
v
#
#
#
INC 2
INC 2
INC 2
INC 2
LD 2
LD 2
LD 2
LD 2
sd 1
sd 1
sd 1
sd 1
sd 1
sd 1
sd 1
sd 1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
0110
e
e
6
e
e
e
e
e
e
e
e
e
e
e
e
e
e
JRC
JRC 4
JRC 4
JRC 4
JRC 4
JRC 4
JRC
JRC 4
JRC 4
JRC 4
JRC 4
JRC 4
JRC 4
JRC 4
JRC
JRC 4
2
1
prc 1
prc 2
prc 1
prc 2
prc 1
prc 2
prc 1
prc
prc 1
prc
prc 1
prc 2
prc 1
prc 2
prc 1
prc
e
JRC
0111
a,(x)
a,(x)
a,nn
a,(x)
a,nn
(x),a
a,(x)
a,nn
a,(x)
a,nn
a,nn
prc
(x)
(x)
7
#
#
#
ADDI
ANDI
SUBI
DEC
ADD
AND
SUB
imm
imm
imm
imm
imm
CPI
INC
LDI
CP
ind
ind
ind
ind
ind
ind
LD
ind
ind
LD
LOW
Mnemonic
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
HI