s29gl128n Meet Spansion Inc., s29gl128n Datasheet - Page 16

• Manufacturer Part Number: s29gl128n
• Description: 3.0 Volt-only Page Mode Flash Memory Featuring 110 Nm Mirrorbit ?rocess Technology
• Manufacturer: Meet Spansion Inc.

14
Requirements for Reading Array Data
Writing Commands/Command Sequences
T o read array data from the outputs, the system must drive the CE# and OE# pins to V
CE# is the power control and selects the device. OE# is the output control and gates array
data to the output pins. WE# should remain at V
The internal state machine is set for reading array data upon device power-up, or after a hard-
ware reset. This ensures that no spurious alteration of the memory content occurs during the
power transition. No command is necessary in this mode to obtain array data. Standard mi-
croprocessor read cycles that assert valid addresses on the device address inputs produce
valid data on the device data outputs. The device remains enabled for read access until the
command register contents are altered.
See
ations table for timing specifications and to
Refer to the DC Characteristics table for the active current specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask
ROM read operation. This mode provides faster read access speed for random locations within
a page. The page size of the device is 8 words/16 bytes. The appropriate page is selected by
the higher address bits A(max)–A3. Address bits A2–A0 in word mode (A2–A-1 in byte mode)
determine the specific word within a page. This is an asynchronous operation; the micropro-
cessor supplies the specific word location.
The random or initial page access is equal to t
(as long as the locations specified by the microprocessor falls within that page) is equivalent
to t
is t
constant and changing the “intra-read page” addresses.
T o write a command or command sequence (which includes programming data to the device
and erasing sectors of memory), the system must drive WE# and CE# to V
The device features an Unlock Bypass mode to facilitate faster programming. Once the de-
vice enters the Unlock Bypass mode, only two write cycles are required to program a word or
byte, instead of four. The “Word Program Command Sequence” section has details on pro-
gramming data to the device using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
page
sector occupies.
Refer to the DC Characteristics table for the active current specification for the write mode.
The AC Characteristics section contains timing specification tables and timing diagrams for
write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one
programming operation. This results in faster effective programming time than the standard
programming algorithms. See
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of
two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster
manufacturing throughput at the factory.
ACC
PACC
Reading Array Data‚ on page 50
16,
or t
. When CE# is de-asserted and reasserted for a subsequent access, the access time
T able 4 on page
CE
. Fast page mode accesses are obtained by keeping the “read-page addresses”
S29GL-N MirrorBit™ Flash Family
34, and
Write Buffer‚ on page 14
T able 5 on page 37
for more information. Refer to the AC Read-Only Oper-
D a t a
Figure 11, on page 78
ACC
S h e e t
IH
or t
.
CE
indicate the address space that each
and subsequent page read accesses
for more information.
for the timing diagram.
IL
S29GL-N_00_B3 October 13, 2006
, and OE# to V
Table 2 on
IH
IL
.
.