s29gl128n Meet Spansion Inc., s29gl128n Datasheet - Page 17

• Manufacturer Part Number: s29gl128n
• Description: 3.0 Volt-only Page Mode Flash Memory Featuring 110 Nm Mirrorbit ?rocess Technology
• Manufacturer: Meet Spansion Inc.

S29GL-N_00_B3 October 13, 2006
Standby Mode
Automatic Sleep Mode
RESET#: Hardware Reset Pin
automatic sleep mode current specification.
If the system asserts V
lock Bypass mode, temporarily unprotects any protected sector groups, and uses the higher
voltage on the pin to reduce the time required for program operations. The system would use
a two-cycle program command sequence as required by the Unlock Bypass mode. Removing
V
pin must not be at V
may result. WP# has an internal pullup; when unconnected, WP# is at V
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect
mode. The system can then read autoselect codes from the internal register (which is sepa-
rate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode.
Refer to the
for more information.
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at
V
are held at V
current is greater. The device requires standard access time (t
device is in either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current
until the operation is completed.
Refer to
The automatic sleep mode minimizes Flash device energy consumption. The device automat-
ically enables this mode when addresses remain stable for t
mode is independent of the CE#, WE#, and OE# control signals. Standard address access
timings provide new data when addresses are changed. While in sleep mode, output data is
latched and always available to the system. Refer to
The RESET# pin provides a hardware method of resetting the device to reading array data.
When the RESET# pin is driven low for at least a period of t
nates any operation in progress, tristates all output pins, and ignores all read/ write
commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data. The operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
the device draws CMOS standby current (I
V
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also
reset the Flash memory, enabling the system to read the boot-up firmware from the Flash
memory.
Refer to the AC Characteristics tables for RESET# parameters and to
for the timing diagram.
HH
IO
SS
±0.3 V , the standby current is greater.
± 0.3 V. (Note that this is a more restricted voltage range than V
from the WP#/ACC pin returns the device to normal operation. Note that the WP#/ACC
DC Characteristics‚ on page 74
IH
Autoselect Mode‚ on page 37
, but not within V
HH
D a t a
HH
for operations other than accelerated programming, or device damage
S29GL-N MirrorBit™ Flash Family
on this pin, the device automatically enters the aforementioned Un-
S h e e t
IO
± 0.3 V , the device is in the standby mode, but the standby
for the standby current specification.
and
CC5
Autoselect Command Sequence‚ on page
). If RESET# is held at V
DC Characteristics‚ on page 74
ACC
RP
, the device immediately termi-
CE
+ 30 ns. The automatic sleep
) for read access when the
IH
Figure 13, on page 79
.) If CE# and RESET#
IH
.
IL
but not within
SS
±0.3 V,
for the
51,
15