ad7853lan Analog Devices, Inc., ad7853lan Datasheet
ad7853lan
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ad7853lan Summary of contents
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... COMP BUF CHARGE REDISTRIBUTION DAC SAR + ADC CONTROL CALIBRATION MEMORY AND CONTROLLER SERIAL INTERFACE / CONTROL REGISTER SYNC SM1 SM2 DIN DOUT SCLK POLARITY . DD World Wide Web Site: http://www.analog.com © Analog Devices, Inc., 1998 DV DD DGND AMODE CLKIN CONVST BUSY SLEEP . DD ...
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AD7853/AD7853L–SPECIFICATIONS External Reference MHz (1.8 MHz B Grade ( +70 C), 1 MHz A and B Grades (– +85 C) for L Version); f CLKIN (AD7853) 100 kHz (AD7853L); SLEEP = Logic High; ...
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Parameter A Version LOGIC OUTPUTS Output High Voltage 2.4 Output Low Voltage, V 0.4 OL Floating-State Leakage Current 10 4 Floating-State Output Capacitance 10 Output Coding CONVERSION RATE Conversion Time 4.6 (18) Track/Hold Acquisition Time 0.4 (1) ...
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AD7853/AD7853L TIMING SPECIFICATIONS Limit MIN (A, B Versions) Parameter 500 CLKIN 4 1 SCLK f CLKIN 4 t 100 4.6 CONVERT 10 (18) ...
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TYPICAL TIMING DIAGRAMS Figures 2 and 3 show typical read and write timing diagrams. Figure 2 shows the reading and writing after conversion in In- terface Modes 2 and 3. To attain the maximum sample rate of 100 kHz (AD7853L) ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents 100 mA will not cause SCR latch-up. Model + 0.3 V AD7853AN DD + 0.3 V AD7853BN DD + 0.3 V AD7853LAN DD + 0.3 V AD7853LBN AD7853AR AD7853BR AD7853LAR AD7853LBR AD7853ARS ...
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Pin Mnemonic Description CONVST 1 Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode and starts conversion. When this input is not used, it should be tied ...
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AD7853/AD7853L TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The end- points of the transfer function are zero scale, a point 1/2 LSB below the first code ...
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ON-CHIP REGISTERS The AD7853/AD7853L powers up with a set of default conditions, and the user need not ever write to the device. In this case the AD7853/AD7853L will operate as a Read-Only ADC. The AD7853/AD7853L still retains the flexibility for ...
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AD7853/AD7853L CONTROL REGISTER The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The control register is selected by putting two 1s in ADDR1 and ADDR0. The ...
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STATUS REGISTER The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The status register is selected by first writing to the control register and putting two 1s ...
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AD7853/AD7853L CALIBRATION REGISTERS The AD7853/AD7853L has ten calibration registers in all, eight for the DAC, one for the offset and one for gain. Data can be writ- ten to or read from all ten calibration registers. In self- and system ...
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START WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1, RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11 CAL REGISTER POINTER IS AUTOMATICALLY RESET READ CAL REGISTER CAL REGISTER POINTER IS AUTOMATICALLY INCREMENTED LAST REGISTER ...
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AD7853/AD7853L CIRCUIT INFORMATION The AD7853/AD7853L is a fast, 12-bit single supply A/D con- verter. The part requires an external 4 MHz/1.8 MHz master capacitors, a CONVST signal to start clock (CLKIN), two C REF conversion and power supply decoupling capacitors. ...
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TYPICAL CONNECTION DIAGRAM Figure 10 shows a typical connection diagram for the AD7853/ AD7853L. The DIN line is tied to DGND so that no data is written to the part. The AGND and the DGND pins are con- nected together ...
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AD7853/AD7853L + 10k V IN 10k V+ – REF REF 50 IC1 10k AD820 V /2 REF V– AD820-3V 10k Figure 13. Analog Input Buffering Input Ranges The analog input range for ...
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REFERENCE SECTION For specified performance recommended that when using an external reference this reference should be between 2.3 V and the analog supply AV . The connections for the relevant DD reference pins are shown in the typical ...
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AD7853/AD7853L – 3.3V/5.0V 100mV p-p SINE WAVE –80 –82 –84 –86 –88 – INPUT FREQUENCY – kHz Figure 22. PSRR vs. Frequency POWER-DOWN OPTIONS The AD7853 provides ...
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Table VI. Power Management Options PMGT1 PMGT0 SLEEP Bit Bit Pin Comment Full Power-Down if Not Cali- brating or Converting (Default Condition After Power-On Normal Operation Normal Operation (Independent of the ...
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AD7853/AD7853L POWER VS. THROUGHPUT RATE The main advantage of a full power-down after a conversion is that it significantly reduces the power consumption of the part at lower throughput rates. When using this mode of operation, the AD7853 is only ...
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Again it is the ratio of these capacitors to the capacitors in the DAC that is critical and the calibration algorithm ensures that this ratio ...
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AD7853/AD7853L System Gain and Offset Interaction The inherent architecture of the AD7853/AD7853L leads to an interaction between the system offset and gain errors when a system calibration is performed. Therefore it is recommended to perform the cycle of a system ...
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SERIAL INTERFACE SUMMARY Table IX details the five interface modes and the serial clock edges from which the data is clocked out by the AD7853/ AD7853L (DOUT Edge) and that the data is latched in on (DIN Edge). The logic ...
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AD7853/AD7853L DETAILED TIMING SECTION Mode 1 (2-Wire 8051 Interface) The read and writing takes place on the DIN line and the con- version is initiated by pulsing the CONVST pin (note that in every write cycle the 2/3 Mode bit ...
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Mode 2 (3-Wire SPI/QSPI Interface Mode) This is the DEFAULT INTERFACE MODE. In Figure 35 below we have the timing diagram for Interface Mode 2 which is the SPI/QSPI interface mode. Here the SYNC input is active low and may ...
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AD7853/AD7853L The most important point about these two modes of operation mode is that the result of the current conversion is clocked out during the same conversion and a write to the part dur- ing this conversion is for the ...
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CONFIGURING THE AD7853/AD7853L AD7853/AD7853L as a Read-Only ADC The AD7853/AD7853L contains fourteen on-chip registers which can be accessed via the serial interface. In the majority of applications it will not be necessary to access all of these regis- ters. Figure ...
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AD7853/AD7853L Writing to the AD7853/AD7853L For accessing the on-chip registers it is necessary to write to the part. To enable Serial Interface Mode 1, the user must also write to the part. Figure 41 through 43 outline flowcharts of how ...
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Interface Mode 1 Configuration Figure 42 shows the flowchart for configuring the part in Interface Mode 1. This mode of operation can only enabled by writing to the control register and setting the 2/3 MODE bit. Reading and writing cannot ...
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AD7853/AD7853L MICROPROCESSOR INTERFACING In many applications, the user may not require the facility of writing to the on-chip registers. The user may just want to hardwire the relevant pins to the appropriate levels and read the conversion result. In this ...
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OPTIONAL 4MHz/1.8MHz 68HC11/L11/ SPI HC16, QSPI SS SCK MISO MASTER IRQ OPTIONAL MOSI DIN AT DGND FOR NO WRITING TO PART DGND FOR HC11, SPI DV FOR HC16, QSPI Figure 46. 68HC11 and 68HC16 Interface ...
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AD7853/AD7853L APPLICATION HINTS Grounding and Layout The analog and digital supplies to the AD7853/AD7853L are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The part has very good immunity to noise ...
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PAGE INDEX Topic FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AD7853/AD7853L PIN 1 0.016 (0.41) PIN 1 0.01 (0.254) 0.006 (0.15) PIN 1 0.008 (0.203) 0.002 (0.050) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Plastic DIP (N-24 0.260 0.001 (6.61 0.03 1.228 (31.19) 1.226 ...