mt48lc2m32b2 Micron Semiconductor Products, mt48lc2m32b2 Datasheet - Page 17

• Manufacturer Part Number: mt48lc2m32b2
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

COMMAND INHIBIT
NO OPERATION (NOP)
LOAD MODE REGISTER
ACTIVE
READ
WRITE
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
The NO OPERATION (NOP) command is used to perform an NOP to an SDRAM that is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
The mode register is loaded via inputs A0–A10. See “Mode Register” on page 12. The
LOAD MODE REGISTER command can only be issued when all banks are idle, and a
subsequent executable command cannot be issued until
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address
provided on inputs A0–A10 selects the row. This row remains active (or open) for
accesses until a PRECHARGE command is issued to that bank. A PRECHARGE
command must be issued before opening a different row in the same bank.
The READ command is used to initiate a burst read access to an active row. The value on
the BA0 and BA1 (B1) inputs selects the bank, and the address provided on inputs A0–A7
selects the starting column location. The value on input A10 determines whether auto
precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the read burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Read data appears on the DQs subject to the logic
level on the DQM inputs two clocks earlier. If a given DQMx signal was registered HIGH,
the corresponding DQs will be High-Z two clocks later; if the DQMx signal was registered
LOW, the corresponding DQs will provide valid data. DQM0 corresponds to DQ0–DQ7,
DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23, and DQM3
corresponds to DQ24–DQ31.
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A0–A7
selects the starting column location. The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the write burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Input data appearing on the DQs is written to the
memory array subject to the DQM input logic level appearing coincident with the data.
If a given DQM signal is registered LOW, the corresponding data will be written to
memory; if the DQM signal is registered HIGH, the corresponding data inputs will be
ignored, and a write will not be executed to that byte/column location.
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
MRD is met.
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Commands