mt4c4m4b1 Micron Semiconductor Products, mt4c4m4b1 Datasheet - Page 8

• Manufacturer Part Number: mt4c4m4b1
• Description: 4 Meg X 4 Fpm Dram
• Manufacturer: Micron Semiconductor Products

NOTES
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. V
9. In addition to meeting the transition rate
10. If CAS# = V
11. If CAS# = V
12. Measured with a load equivalent to two TTL
13. If CAS# is LOW at the falling edge of RAS#, Q
14. The
15. The
4 Meg x 4 FPM DRAM
D49_5V.p65 – Rev. 5/00
f = 1 MHz.
rates. Specified values are obtained with
minimum cycle time and the outputs open.
indicate cycle time at which proper operation
over the full temperature range is ensured.
up, followed by eight RAS# refresh cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper
device operation is ensured. The eight RAS# cycle
wake-ups should be repeated any time the
refresh requirement is exceeded.
measuring timing of input signals. Transition
times are measured between V
between V
specification, all input signals must transit
between V
a monotonic manner.
from the last valid READ cycle.
gates, 100pF and V
will be maintained from the previous cycle. To
initiate a new cycle and clear the data-out
buffer, CAS# must be pulsed HIGH for
t
only. If
t
trolled exclusively by
longer applied). With or without the
t
t
only. If
t
RCD (MAX) was specified as a reference point
RCD (MAX) limit, then access time was con-
AA and
RAD (MAX) was specified as a reference point
RAD (MAX) limit, then access time was con-
CC
IH
is dependent on output loading and cycle
(MIN) and V
t
t
RCD (MAX) limit is no longer specified.
RAD (MAX) limit is no longer specified.
t
t
RCD was greater than the specified
t
RAD was greater than the specified
CAC must always be met.
IL
IH
IH
IL
and V
and V
, data output may contain data
, data output is High-Z.
IL
IH
(MAX) are reference levels for
IL
OL
).
(or between V
= 0.8V and V
t
CAC (
t
T = 5ns.
SS
CC
t
.
RAC [MIN] no
IH
= +3.3V or 5.0V;
and V
IL
OH
and V
t
= 2V.
IL
RCD limit,
t
CP.
(or
IH
t
REF
) in
8
16. Either
17.
18.
19. These parameters are referenced to CAS# leading
20. If OE# is tied permanently LOW, LATE WRITE,
21. A HIDDEN REFRESH may also be performed
22. The 3ns minimum is a parameter guaranteed by
23. Column address changed once each cycle.
24. V
trolled exclusively by
longer applied). With or without the
(MAX) limit,
be met.
cycle.
t
output achieves the open circuit condition and
is not referenced to V
t
restrictive operating parameters.
EARLY WRITE cycles.
apply to READ-MODIFY-WRITE cycles. If
cycle and the data output will remain an open
circuit throughout the entire cycle. If
t
³
WRITE and the data output will contain data
read from the selected cell. If neither of the
above conditions is met, the state of data-out is
indeterminate. OE# held HIGH and WE# taken
LOW after CAS# goes LOW result in a LATE
WRITE (OE#-controlled) cycle.
t
WRITE cycle.
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
or READ-MODIFY-WRITE operations are not
permissible and should not be attempted.
after a WRITE cycle. In this case, WE# = LOW
and OE# = HIGH.
design.
width £ 10ns, and the pulse width cannot be
greater than one third of the cycle rate. V
undershoot: V
10ns, and the pu lse width cannot be greater
than one third of the cycle rate.
OFF (MAX) defines the time at which the
WCS,
RWD (MIN),
CWD, and
IH
t
t
WCS (MIN), the cycle is an EARLY WRITE
CWD (MIN), the cycle is a READ-MODIFY-
overshoot: V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
RCH or
RWD,
t
AWD are not applicable in a LATE
t
AA,
t
t
IL
AWD ³
AWD, and
t
RRH must be satisfied for a READ
(MIN) = -2V for a pulse width £
IH
t
(MAX) = V
RAC, and
OH
t
t
AA (
RWD,
t
AWD (MIN), and
or V
t
t
CWD are not
RAC and
OL
t
CC
t
FPM DRAM
CAC must always
AWD, and
.
4 MEG x 4
t
WCS,
+ 2V for a pulse
t
WCS applies to
©2000, Micron Technology, Inc.
OBSOLETE
t
CAC no
t
t
RWD ³
t
RAD
RWD,
IL
t
t
CWD
t
CWD
WCS