mc100es6535 Integrated Device Technology, mc100es6535 Datasheet

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mc100es6535

Manufacturer Part Number
mc100es6535
Description
Lvcmos-input Lvpecl-output 1-ghz 3.3v 1 4 Fanout Buffer
Manufacturer
Integrated Device Technology
Datasheet
IDT™ 3.3V LVCMOS to LVPECL 1:4 Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
3.3V LVCMOS to LVPECL 1:4 Fanout
Buffer
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3.3V LVCMOS to LVPECL 1:4
Fanout Buffer
LVCMOS to LVPECL fanout buffer. The ES6535 has two selectable
inputs that allow LVCMOS or LVTTL input levels which translate to
LVPECL outputs.
eliminate runt pulses on the outputs during asynchronous assertion/
deassertion of the clock enable pin. The ES6535 is ideal for high
performance clock distribution applications.
Features
• 4 differential LVPECL outputs
• 2 selectable LVCMOS/LVTTL inputs
• 1 GHz maximum output frequency
• Translates LVCMOS/LVTTL levels to LVPECL levels
• 30 ps maximum output skew
• 190 ps part-to-part skew
• 3.3 V operating range
• 20-lead TSSOP package
• Ambient temperature range -40 C to +85 C
© Motorola, Inc. 2004
The MC100ES6535 is a low skew, high performance 3.3 V 1-to-4
CLK_EN
CLK0
CLK1
CLK_SEL
The clock enable is internally synchronized to
0
1
Figure 1. Logic Diagram
D
LE
Freescale Semiconductor, Inc.
Q
For More Information On This Product,
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
1
V
CLK_EN
CLK_SEL
CLK0
nc
CLK1
nc
nc
nc
V
MC100ES6535DT
MC100ES6535DTR2
EE
CC
Device
ORDERING INFORMATION
20-LEAD TSSOP PACKAGE
Figure 2. 20-Lead Pinout (Top View)
10
1
2
3
4
5
6
7
8
9
MC100ES6535
CASE 948E
DT SUFFIX
Order number: MC100ES6535
MC100ES6535
TSSOP-20
TSSOP-20
DATA SHEET
Package
20
19
18
17
16
15
14
13
12
11
Rev 2, 05/2004
MC100ES6535
Q0
Q0
V
Q1
Q1
Q2
Q2
V
Q3
Q3
CC
CC

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mc100es6535 Summary of contents

Page 1

... SEMICONDUCTOR TECHNICAL DATA 3.3V LVCMOS to LVPECL 1:4 Fanout 3.3V LVCMOS to LVPECL 1:4 Buffer Fanout Buffer The MC100ES6535 is a low skew, high performance 3.3 V 1-to-4 LVCMOS to LVPECL fanout buffer. The ES6535 has two selectable inputs that allow LVCMOS or LVTTL input levels which translate to LVPECL outputs. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin ...

Page 2

... LVPECL differential output pair LVPECL differential output pair LVPECL differential output pair a Q0:Q3 CLK0 Disabled; LOW CLK1 Disabled; LOW CLK0 Enabled CLK1 Enabled Q0:Q3 HIGH LOW 2 2 For More Information On This Product, Description Outputs Q0:Q3 Disabled; HIGH Disabled; HIGH Enabled Enabled TIMING SOLUTIONS NETCOM MC100ES6535 ...

Page 3

... Max Min Typ Max 35 45 –800 V –1200 V –970 V –750 –1250 V –2000 V –1680 V –1300 Max Min Typ Max 150 150 -1.2 -1.2 0.3 2.0 V 0.3 CC+ CC+ 0.8 0.8 NETCOM Units Unit Unit MC100ES6535 MOTOROLA ...

Page 4

... For More Information On This Product Min Typ Max Min Typ 1 175 360 550 200 380 190 1 350 750 350 750 50 400 50 D Receiver Device TIMING SOLUTIONS NETCOM Unit Max 1 GHz 600 190 400 ps MC100ES6535 ...

Page 5

... INCHES DIM MIN MAX MIN A 6.40 6.60 0.252 B 4.30 4.50 0.169 C --- 1.20 --- D 0.05 0.15 0.002 F 0.50 0.75 0.020 -W- 0.65 BSC 0.026 BSC G H 0.27 0.37 0.011 J 0.09 0.20 0.004 J1 0.09 0.16 0.004 K 0.19 0.30 0.007 K1 0.19 0.25 0.007 6.40 BSC L 0.252 BSC M 0˚ 8˚ 0˚ NETCOM MAX 0.260 0.177 0.047 0.006 0.030 0.015 0.008 0.006 0.012 0.010 8˚ MC100ES6535 MOTOROLA ...

Page 6

... MPC92459 MC100ES6535 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer 3.3V LVCMOS to LVPECL 1:4 Fanout Buffer INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. ...

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