mc100es6535 Integrated Device Technology, mc100es6535 Datasheet - Page 2

• Manufacturer Part Number: mc100es6535
• Description: Lvcmos-input Lvpecl-output 1-ghz 3.3v 1 4 Fanout Buffer
• Manufacturer: Integrated Device Technology

IDT™ 3.3V LVCMOS to LVPECL 1:4 Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES6535
a
a
MOTOROLA
Table 1. PIN DESCRIPTION
Table 2. CONTROL INPUT FUNCTION TABLE
Table 3. CLOCK INPUT FUNCTION TABLE
MC100ES6535
3.3V LVCMOS to LVPECL 1:4 Fanout Buffer
10, 13, 18
CLK0 or CLK1
Number
5, 7, 8, 9
of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3.
Pullup and Pulldown refer to internal input resistors.
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge. In the active mode, the state
11, 12
14, 15
16, 17
19, 20
CLK_EN
1
2
3
4
6
Inputs
0
0
1
1
0
1
CLK_SEL
CLK_EN
Q3, Q3
Q2, Q2
Q1, Q1
Q0, Q0
Name
CLK0
CLK1
V
V
nc
CLK_SEL
CC
EE
Inputs
Q0:Q3
HIGH
LOW
0
1
0
1
Outputs
Unused
Output
Output
Output
Output
Power
Power
Input
Input
Input
Input
Selected Source
Q0:Q3
HIGH
LOW
Freescale Semiconductor, Inc.
CLK0
CLK1
CLK0
CLK1
For More Information On This Product,
Type
a
Pulldown
Pulldown
Pulldown
Pullup
a
a
a
a
Disabled; LOW
Disabled; LOW
Negative supply pin
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, Q outputs are forced high.
LVCMOS/LVTTL interface levels
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0 input.
LVCMOS/LVTTL interface levels
LVCMOS/LVTTL clock input
LVCMOS/LVTTL clock input
No connect
Positive supply pin
LVPECL differential output pair
LVPECL differential output pair
LVPECL differential output pair
LVPECL differential output pair
2
Enabled
Enabled
Q0:Q3
2
Outputs
Description
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
Q0:Q3
TIMING SOLUTIONS
MC100ES6535
NETCOM