adf4207 Analog Devices, Inc., adf4207 Datasheet

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adf4207

Manufacturer Part Number
adf4207
Description
Dual Rf Pll Frequency Synthesizers
Manufacturer
Analog Devices, Inc.
Datasheet
a
OSC
CLOCK
RF2
RF2
RF1
RF1
OSC
DATA
OUT
IN
IN
IN
IN
LE
IN
A
B
A
B
OSCILLATOR
REGISTER
22-BIT
DATA
N = BP + A
N = BP + A
PRESCALER
PRESCALER
RF2
RF1
SDOUT
DGND
FUNCTIONAL BLOCK DIAGRAM
V
DD
1
RF1
B-COUNTER
A-COUNTER
B-COUNTER
11-BIT RF2
A-COUNTER
11-BIT RF1
AGND
6-BIT RF2
6-BIT RF1
Dual RF PLL Frequency Synthesizers
V
R-COUNTER
R-COUNTER
14-BIT RF1
DD
14-BIT RF2
2
RF1
DGND
GENERAL DESCRIPTION
The ADF4206 family of dual frequency synthesizers can be
used to implement local oscillators in the upconversion and
downconversion sections of wireless receivers and transmitters.
Each synthesizer consists of a low-noise digital PFD (Phase
Frequency Detector), a precision charge pump, a programmable
reference divider, programmable A and B counters and a dual-
modulus prescaler (P/P + 1). The A (6-bit) and B (11-bit)
counters, in conjunction with the dual modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R Counter), allows selectable REFIN frequen-
cies at the PFD input. The on-chip oscillator circuitry allows
the reference input to be derived from crystal oscillators.
A complete PLL (Phase-Locked Loop) can be implemented if
the synthesizers are used with an external loop filter and VCOs
(Voltage Controlled Oscillators).
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V
to 5.5 V and can be powered down when not in use.
V
P
1
ADF4206/ADF4207/ADF4208
RF2
ADF4206/ADF4207/ADF4208
COMPARATOR
COMPARATOR
AGND
V
PHASE
P
PHASE
2
RF2
OUTPUT
DETECT
DETECT
LOCK
LOCK
MUX
RF2
RF1
CHARGE
CHARGE
PUMP
PUMP
MUXOUT
CP
CP
RF2
RF1

Related parts for adf4207

adf4207 Summary of contents

Page 1

... RF2 R-COUNTER SDOUT 14-BIT RF1 R-COUNTER 11-BIT RF1 B-COUNTER RF1 PRESCALER 6-BIT RF1 A-COUNTER DGND AGND DGND RF1 RF2 RF1 ADF4206/ADF4207/ADF4208 PHASE COMPARATOR CHARGE CP RF2 PUMP RF2 LOCK DETECT OUTPUT MUXOUT MUX RF1 LOCK DETECT CHARGE CP RF1 PUMP PHASE ...

Page 2

... IN LOGIC OUTPUTS V , Output High Voltage Output Low Voltage OL POWER SUPPLIES ADF4206 ADF4207 ADF4208 ADF4206 ADF4207 ADF4208 ADF4206 ADF4207 ADF4208 Low-Power Sleep Mode = AGND = DGND = ...

Page 3

... The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). 8 The phase noise is measured kHz unless otherwise noted. The phase noise is measured with the EVAL-ADF4206/ADF4207EB or the EVAL-AD4208EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (f ...

Page 4

... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4206/ADF4207/ADF4208 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

Page 5

... CMOS or TTL DD PIN CONFIGURATIONS RF2 DGND RF2 RF2 IN LE DATA CLK ADF4206/ADF4207/ADF4208 . V 1 should have a value of between 2.7 V and RF1 RF2 DD 2 must have the same potential TSSOP ...

Page 6

... ADF4206/ADF4207/ADF4208 –Typical Performance Characteristics FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD GHz FREQ MAGS11 ANGS11 FREQ MAGS11 0.0 0.957111193 –3.130429321 1.35 0.816886959 0.15 0.963546793 –6.686426265 1.45 0.825983016 0.25 0.953621785 –11.19913586 1.55 0.791737125 0.35 0.953757706 –15.35637483 1.65 0.770543186 0.45 0.929831379 –20.3793432 1.75 0.793897072 0.55 0.908459709 –22.69144845 1.85 0.745765233 0.65 0.897303634 –27.07001443 1 ...

Page 7

... I = 5mA CP PFD FREQUENCY = 30kHz LOOP BANDWIDTH = 3kHz RES. BANDWIDTH = 3Hz VIDEO BANDWIDTH = 3Hz SWEEP = 255 SECONDS POSITIVE PEAK DETECT MODE –79.6dBc –200k 1750M 40k 80k FREQUENCY – Hz ADF4206 ADF4207 ADF4208 100 1000 10000 100 TEMPERATURE – C ...

Page 8

... PHASE DETECTOR FREQUENCY – kHz 3 2 2.0 1.5 1.0 0 100 ADF4207 5 4 ADF4206 ADF4207 ADF4208 1000 10000 = 100 150 PRESCALER OUTPUT FREQUENCY – MHz ADF4208 32/33 64/65 PRESCALER VALUE 200 ...

Page 9

... PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R counter and N counter ( and produces an output proportional to the phase and frequency difference between them. Figure simplified schematic. ADF4206/ADF4207/ADF4208 f = [(P × × VCO REFIN ...

Page 10

... ADF4206/ADF4207/ADF4208 DIVIDER CLR1 DELAY U3 ELEMENT CLR2 DOWN DIVIDER R DIVIDER N DIVIDER CP OUTPUT The PFD includes a delay element which sets the width of the antibacklash phase. The typical value for this is in the ADF4206 family is 3 ns. The pulse ensures that there is no deadzone in the PFD transfer function and minimizes phase noise and refer- ence spurs ...

Page 11

... P9 R14 R13 P12 11-BIT B COUNTER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 P16 P14 B11 B10 ADF4206/ADF4207/ADF4208 RF2 REFERENCE COUNTER LATCH 14-BIT REFERENCE COUNTER, R DB13 DB12 DB11 DB10 DB9 DB8 DB7 R12 R11 R10 RF2 AB COUNTER LATCH ...

Page 12

... ADF4206/ADF4207/ADF4208 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 R14 POLARITY 0 NEGATIVE 1 POSITIVE 1. 4.375 mA P2 CHARGE PUMP OUTPUT 0 NORMAL 1 THREE-STATE P12 P11 FROM RF1 R LATCH ...

Page 13

... P6 RF2 PRESCALER 0 64/65 1 32/33 P7 RF2 SECTION 0 NORMAL OPERATION 1 POWER-DOWN ADF4206/ADF4207/ADF4208 Table IV. RF2 AB Counter Latch Map RF2 AB COUNTER LATCH DB13 DB12 DB11 DB10 DB9 DB8 DB7 ...

Page 14

... ADF4206/ADF4207/ADF4208 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 P12 P9 R14 P11 P10 P13 P9 PD POLARITY 0 NEGATIVE 1 POSITIVE P13 1. 4.375 mA P10 CHARGE PUMP OUTPUT 0 NORMAL 1 THREE-STATE P4 P3 P12 P11 FROM RF2 R LATCH ...

Page 15

... P14 RF1 PRESCALER 0 64/65 1 32/33 P16 RF1 SECTION 0 NORMAL OPERATION 1 POWER-DOWN ADF4206/ADF4207/ADF4208 RF1 AB COUNTER LATCH DB12 DB11 DB10 DB9 DB8 DB7 ...

Page 16

... ADF4206/ADF4207/ADF4208 PROGRAM MODES Table III and Table V show how to set up the Program Modes in the ADF420x family. The following should be noted: 1. RF2 and RF1 Analog Lock Detect indicate when the PLL is in lock. When the loop is locked and either RF2 or RF1 Analog Lock Detect is selected, the MUXOUT pin will show a logic high with narrow low-going pulses ...

Page 17

... DECOUPLING CAPACITORS (22 F/10pF THE ADF4207, AND THE VCOs HAVE BEEN CC OMITTED FROM THE DIAGRAM TO AID CLARITY. ADF4206/ADF4207/ADF4208 Programmable RF1 AB Counter If control bits (C2, C1) are (1, 1), then the data in the input register is used to program the RF1 AB counter. The AB counter consists of a 6-bit swallow counter (A counter) and 11-bit programmable counter (B counter) ...

Page 18

... ADF4206/ADF4207/ADF4208 APPLICATIONS SECTION Local Oscillator for GSM Handset Receiver Figure 7 shows the ADF4207 being used in a classic superhet- erodyne receiver to provide the required LOs (Local Oscillators). In this circuit, the reference input signal is applied to the circuit at OSC and is being generated MHz Crystal Oscillator. ...

Page 19

... INTERFACING The ADF4206/ADF4207/ADF4208 family has a simple SPI- compatible serial interface for writing to the device. SCLK, SDATA, and LE (Latch Enable) control the data transfer. When LE goes high, the 22 bits that have been clocked into the input register on each rising edge of SCLK will be transferred to the appropriate latch ...

Page 20

... ADF4206/ADF4207/ADF4208 Thin Shrink Small Outline Package (TSSOP) (RU-16) 0.201 (5.10) 0.193 (4.90 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25 PIN 1 0.006 (0.15) 0.0433 (1.10) MAX 0.002 (0.05) 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) SEATING BSC 0.0075 (0.19) PLANE 0.0035 (0.090) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Thin Shrink Small Outline Package (TSSOP) ...

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