adf4207 Analog Devices, Inc., adf4207 Datasheet - Page 9

• Manufacturer Part Number: adf4207
• Description: Dual Rf Pll Frequency Synthesizers
• Manufacturer: Analog Devices, Inc.

CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 2. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2
are opened. Typical recommended external components are
shown in Figure 2.
RF INPUT STAGE
The RF input stage is shown in Figure 3. It is followed by a
2-stage limiting amplifier to generate the CML clock levels needed
for the prescaler.
PRESCALER
The dual modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = BP + A). This prescaler, operating at CML levels, takes
the clock from the RF input stage and divides it down to a man-
ageable frequency for the CMOS A and B counters. It is based
on a synchronous 4/5 core.
The prescaler is selectable. Both RF1 and RF2 can be set to
either 32/33 or 64/65. DB20 of the AB counter latch selects
the value. See Tables IV and VI.
30pF
30pF
18k
RF
RF
IN
IN
OSC
GENERATOR
A
B
OSC
OUT
BIAS
IN
NC
POWER-DOWN
SW1
CONTROL
2k
NO
NC
1.6V
SW2
SW3
2k
100k
AGND
AV
DD
BUFFER
TO R
COUNTER
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feed-
back counter. The devices are guaranteed to work when the
prescaler output is 200 MHz or less.
Pulse Swallow Function
The A and B counters, in conjunction with the dual modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
f
P
B
A
f
R
R COUNTER
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383
are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and
frequency difference between them. Figure 5 is a simplified
schematic.
VCO
REFIN
INPUT STAGE
= Output frequency of external voltage controlled
= Preset modulus of dual modulus prescaler
= Preset Divide Ratio of binary 11-bit counter
= Preset Divide Ratio of binary 6-bit A counter
= Output frequency of the external reference frequency
= Preset divide ratio of binary 14-bit programmable
FROM RF
oscillator (VCO).
(32/33, 64/65).
(1 to 2047).
(0 to 63).
oscillator.
reference counter (1 to 16383).
ADF4206/ADF4207/ADF4208
f
N DIVIDER
VCO
MODULUS
CONTROL
N = BP + A
PRESCALER
P/P + 1
= [(P × B) + A] × f
LOAD
LOAD
COUNTER
COUNTER
11-BIT B
6-BIT A
REFIN
/R
TO PFD