mc74lvq573 Freescale Semiconductor, Inc, mc74lvq573 Datasheet

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mc74lvq573

Manufacturer Part Number
mc74lvq573
Description
Low-voltage Quiet Cmos Octal Transparent Latch Flow Through Pinout
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Voltage Quiet CMOS
Octal Transparent Latch
Flow Through Pinout
(3-State, Non-Inverting)
transparent latch operating from a 2.7 to 3.6V supply. The MC74LVQ573
is suitable for TTL level bus oriented applications where a memory
element is required.
outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs
enters the latches. In this condition, the latches are transparent, i.e., a
latch output will change state each time its D input changes. When LE is
LOW, the latches store the information that was present on the D inputs a
setup time preceding the HIGH–to–LOW transition of LE. The 3–state
standard outputs are controlled by the Output Enable (OE) input. When
OE is LOW, the standard outputs are enabled. When OE is HIGH, the
standard outputs are in the high impedance state, but this does not
interfere with new data entering into the latches. The LCX573 flow
through design facilitates easy PC board layout.
11/95
Motorola, Inc. 1995
Designed for 2.7 to 3.6V V CC Operation – Ideal for Low Power/Low
Noise Applications
Guaranteed Simultaneous Switching Noise Level and Dynamic
Threshold Performance
Guaranteed Skew Specifications
Guaranteed Incident Wave Switching into 75Ω
Low Static Supply Current (10µA) Substantially Reduces System Power
Requirements
Latchup Performance Exceeds 500mA
ESD Performance: Human Body Model >2000V
The MC74LVQ573 is a high performance, non–inverting octal
The MC74LCX573 contains 8 D–type latches with 3–state standard
V CC
OE
20
1
O0
D0
19
2
O1
D1
18
3
Pinout: 20–Lead (Top View)
O2
D2
17
4
O3
D3
16
5
O4
D4
15
6
1
O5
D5
14
7
O6
13
D6
8
O7
D7
12
9
GND
LE
11
10
PIN NAMES
Pins
OE
LE
D0–D7
O0–O7
REV 0
20
20
20
20
TRANSPARENT LATCH
MC74LVQ573
LVQ
1
1
1
LOW–VOLTAGE
1
Function
Output Enable Input
Latch Enable Input
Data Inputs
3–State Latch Outputs
CMOS OCTAL
PLASTIC SOIC EIAJ
PLASTIC TSSOP
PLASTIC SSOP
CASE 751D–04
CASE 940C–03
PLASTIC SOIC
CASE 948E–02
CASE 967–01
DW SUFFIX
SD SUFFIX
DT SUFFIX
M SUFFIX

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mc74lvq573 Summary of contents

Page 1

... Flow Through Pinout (3-State, Non-Inverting) The MC74LVQ573 is a high performance, non–inverting octal transparent latch operating from a 2.7 to 3.6V supply. The MC74LVQ573 is suitable for TTL level bus oriented applications where a memory element is required. The MC74LCX573 contains 8 D–type latches with 3–state standard outputs ...

Page 2

... MC74LVQ573 INTERNAL INPUTS LATCHES High Voltage Level High Voltage Level One Setup Time Prior to the Latch Enable High–to–Low Transition Low Voltage Level Low Voltage Level One Setup Time Prior to the Latch Enable High– ...

Page 3

... 50µA 2. 3.6V 12mA 2. 3.6V GND V I (OE GND 3.6V; V OLD = 0.8V Max 3.6V; V OHD = 2.0V Min 2. 3.6V GND 3 MC74LVQ573 Condition Unit V V Output in HIGH or LOW State –0. 0. –0. ...

Page 4

... MC74LVQ573 DYNAMIC SWITCHING CHARACTERISTICS ( 3.3V) Symbol Characteristic V OLP Dynamic LOW Peak Voltage (Note 1) V OLV Dynamic LOW Valley Voltage (Note 1) V IHD High Level Dynamic Input Voltage (Note 2) V ILD Low Level Dynamic Input Voltage (Note 2) 1. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW. The remaining output is measured in the LOW state. 2. Number of data inputs is defined as “ ...

Page 5

... PULSE WIDTH SETUP AND HOLD TIMES 2.5ns, 10 1MHz 500ns except when noted Figure 1. AC Waveforms V CC DUT TEST Figure 2. Test Circuit 5 MC74LVQ573 PHL ...

Page 6

... MC74LVQ573 –A – –B – 0.010 (0.25 SEATING G K PLANE 0.13 (0.005) 0.10 (0.004) M MOTOROLA OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D–04 ISSUE 0.010 (0.25 –T M – ...

Page 7

... DETAIL DETAIL E 7 MC74LVQ573 NOTES: 13 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 14 CONTROLLING DIMENSION: MILLIMETER. 15 DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 16 DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION ...

Page 8

... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 *MC74LVQ573/D* 8 MC74LVQ573/D ECLinPS and ECLinPS Lite DL140 — Rev 3 ...

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