cs5364 Cirrus Logic, Inc., cs5364 Datasheet
cs5364
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cs5364 Summary of contents
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... Independent Power-Down Control per Channel Pair VD 3 Control Interface Configuration I2C, SPI Registers or Pins Decimation High Pass Filter Filter Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved) CS5364 ® or SPI™ Control VLC 1 Device Control Serial Digital Audio Out Audio PCM or TDM VLS 1 ...
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... In addition, an on-chip oscillator driver provides clocking flexibility and simplifies design. The CS5364 is the industry’s first audio A/D to support a high-speed TDM interface which provides a serial output of 4 channels of audio data with sample rates up to 216 kHz within a single data stream. It further reduces layout complexity and relieves input/output constraints in digital signal processors ...
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... Overflow Detection ......................................................................................................................... 27 4.9.1 Overflow in Stand-Alone Mode .............................................................................................. 27 4.9.2 Overflow in Control Port Mode .............................................................................................. 27 4.10 Analog Connections ..................................................................................................................... 28 4.11 Optimizing Performance in TDM Mode ........................................................................................ 29 4.12 DC Offset Control ......................................................................................................................... 29 4.13 Control Port Operation .................................................................................................................. 30 4.13.1 SPI Mode ............................................................................................................................. 30 4.13.2 I²C Mode .............................................................................................................................. 31 5. REGISTER MAP ................................................................................................................................... 32 5.1 Register Quick Reference ............................................................................................................. 32 5.2 00h (REVI) Chip ID Code & Revision Register ............................................................................... 32 DS625F3 CS5364 3 ...
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... FILTER PLOTS ..................................................................................................................................... 36 7. PARAMETER DEFINITIONS ................................................................................................................ 39 8. PACKAGE DIMENSIONS ................................................................................................................... 40 THERMAL CHARACTERISTICS ....................................................................................................... 40 9. ORDERING INFORMATION ................................................................................................................ 41 10. REVISION HISTORY ......................................................................................................................... 41 LIST OF FIGURES Figure 1. CS5364 Pinout ............................................................................................................................. 6 Figure 2. Typical Connection Diagram ........................................................................................................ 9 Figure 3. I²S/LJ Timing .............................................................................................................................. 15 Figure 4. TDM Timing ............................................................................................................................... 16 Figure 5. I²C Timing .................................................................................................................................. 17 Figure 6. SPI Timing ................................................................................................................................. 18 Figure 7. Crystal Oscillator Topology ........................................................................................................ 20 Figure 8 ...
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... Table 8. Frequencies for 48 kHz Sample Rate using TDM ....................................................................... 25 Table 9. Frequencies for 96 kHz Sample Rate using TDM ....................................................................... 26 Table 10. Frequencies for 96 kHz Sample Rate using TDM ..................................................................... 26 Table 11. Frequencies for 192 kHz Sample Rate using TDM ................................................................... 26 Table 12. Frequencies for 192 kHz Sample Rate using TDM ................................................................... 26 DS625F3 CS5364 5 ...
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... AIN2+ 1 AIN2- 2 GND REF_GND 5 FILT GND GND 11 AIN4+ 12 AIN4 CS5364 Figure 1. CS5364 Pinout CS5364 36 OVFL 35 VLC 34 CLKMODE GND 31 TDM 30 SDOUT1/TDM 29 GND VLS 28 27 SDOUT2 TSTO 26 SCLK 25 DS625F3 ...
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... Digital Power (Input) - Positive power supply for the digital section. VLC 35 Control Port Interface Power - Positive power for the control port interface. OVFL 36 Overflow (Output, open drain) - Detects an overflow condition on both left and right channels. RST 41 Reset (Input) - The device enters a low power mode when low. DS625F3 Pin Description CS5364 7 ...
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... SPI Format CDOUT (Output) - Acts as an output only data pin. MCLK Divider (Input) - This pin is ignored in Control Port Mode, and the same functionality is MDIV 42 obtained from the corresponding bit in the Global Control Register. Note: Should be connected to GND when using the part in Control Port Mode. 8 CS5364 DS625F3 ...
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... DIF0/AD0/CS RST MDIV CLKMODE CS5364 VLS A/D CONVERTER SDOUT1/TDM SDOUT2 TDM RESERVED LRCK/FS SCLK MCLK VX XTI XTO GND 3, 8,10, 15, 16, 17, 18, 19, 29, 32, 43, 44, 45, 46 Figure 2. Typical Connection Diagram CS5364 +5V to 3.3V 35 +5V to 1.8V μF 0. Power Down 38 and Mode Settings +5V to 1.8V μF 0.01 30 ...
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... Positive Control Logic VLC (-CQZ (-DQZ Symbol Positive Analog VA Positive Crystal VX Positive Digital VD Positive Serial Logic VLS Positive Control Logic VLC IND stg Symbol MCLK t clkhl CS5364 Min Typ Max 4.75 5.0 4.75 5.0 3.14 3.3 5.25 1 1.71 3.3 1.71 3.3 - -40 - 105 Min Typ Max -0.3 - +6.0 +10 -10 VA+0.3 -0.3 - VL+0 ...
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... VLS, VLC, All Supplies = Symbol Min %VLS/VLC V IH %VLS/VLC V IL %VLS/VLC V OH %VLS/VLC V OL logic pins only I in Symbol Min PSRR CS5364 Typ Max - 500 - - 510 580 - 360 419 - 2 ...
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... THD+N - -60 dB -1dB A-weighted 108 unweighted 105 - -1 dB -20 dB THD+N - -60 dB -1dB - - -5 - HPF enabled 0 HPF disabled - 1.07*VA - CMRR - CS5364 = 25° C. Full-scale input A Typ Max Unit 114 - dB 111 - -105 -99 - -51 -45 114 111 - dB 108 -105 -99 - -51 -45 -102 - 114 ...
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... A-weighted 106 unweighted 103 - -1 dB -20 dB THD A-weighted 106 unweighted 103 - -1 dB -20 dB THD HPF enabled 0 HPF disabled - 1.02*VA CMRR - CS5364 Typ Max Unit 114 - dB 111 -105 -97 - -51 -45 114 111 - dB 108 -105 -97 - -51 -45 -102 - 114 111 - dB ...
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... OVFL time-out on overrange condition 14 Symbol Min (-0.1 dB) 0 -0.035 0.58 - (-0.1 dB) 0 -0.035 0.68 - (-0.1 dB) 0 -0.035 0. -0. pF, timing threshold is 50% of VLS. L Symbol Min - Fs = 44.1 kHz Fs = 192 kHz CS5364 Typ Max Unit 0.47 Fs 0.035 12/Fs s 0.45 Fs 0.035 9/Fs s 0.24 Fs 0.035 5/ ...
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... HOLD2 t HOLD2 t HOLD2 Section 4.6.3 "Master Mode Clock Dividers" on page Section 4.7 Master and Slave Clock Frequencies on page t PERIOD t t HOLD1 SET UP1 channel channel t SET UP2 data data Figure 3. I²S/LJ Timing CS5364 Min Typ Max 108 108 216 64*Fs - 64*Fs 72 ...
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... SCLK rising t HOLD2 Section 4.6.3 "Master Mode Clock Dividers" on page Section 4.7 Master and Slave Clock Frequencies on page t t PERIOD HIGH1 t HIGH2 t SETUP1 new frame t t SETUP2 HOLD2 data Figure 4. TDM Timing CS5364 Min Typ Max 108 108 - 216 - 256* ...
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... Figure 5. I²C Timing CS5364 Min Max - 100 600 4.7 4.0 4.7 - 4.0 4.7 0 600 - 1 - 300 4.7 - 300 1000 , of SCL Stop Sta ...
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... Symbol f sck t srs t css t csh t scl t sch t dsu (Note (Note (Note sch scl dsu Figure 6. SPI Timing CS5364 Min Max Units 0 6.0 MHz μs 1 100 t csh t r2 DS625F3 ...
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... Control Port Mode. To use the CS5364 in Stand-Alone Mode, the configuration pins must be held in a stable state, at valid logic levels, and RST must be asserted until the power supplies and clocks are stable and valid. More informa- tion on the reset function is available in 4 ...
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... Master Clock Source The CS5364 requires a Master Clock that can come from one of two sources: an on-chip crystal oscillator driver or an externally generated clock. 4.3.1 On-Chip Crystal Oscillator Driver When using the on-board crystal oscillator driver, the XTI pin (pin 21) is the input for the Master Clock (MCLK) to the device ...
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... To ensure synchronous sampling in applications where multiple ADCs are used, the MCLK and LRCK must be the same for all CS5364 devices in the system. If only one master clock source is needed, one solution is to place one CS5364 in Master Mode, and slave all of the other devices to the one master, as illustrated in Figure 9 ...
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... CS5364 will fill the longer frame with trailing zeros. If fewer than 24 SCLK cycles per channel are received from a master, the CS5364 will truncate the serial data output to the number of SCLK cycles received. For a complete overview of serial audio interface formats, please refer to Cirrus Logic Ap- plication Note AN282 ...
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... Speed Modes 4.6.1 Sample Rate Ranges CS5364 supports sampling rates from 2 kHz to 21 kHz, divided into three ranges: 2 kHz - 54 kHz, 54 kHz - 108 kHz, and 108 kHz - 216 kHz. These sampling speed modes are called Single-Speed Mode (SSM), Double-Speed Mode (DSM), and Quad-Speed Mode (QSM), respectively. ...
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... The external MCLK is subject to clock dividers as set by the clock divider pins in Stand-Alone Mode or the clock divider bits in Control Port Mode. The CS5364 compares the divided- down, internal MCLK to the incoming LRCK/FS and sets the speed mode based on the MCLK/LRCK ratio ...
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... SSM kHz ÷4 ÷3 ÷2 49.152 36.864 24.567 12.288 12.288 12.288 1024 768 512 256 256 256 CS5364 ÷1.5 ÷1 18.384 12.288 3.072 3.072 384 256 64 64 ÷1.5 ÷1 18.384 12.288 6.144 6.144 192 128 64 64 ÷ ...
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... QSM Fs = 192 kHz ÷ 49.152 - - 49.152 - - 256 - - 256 - - QSM Fs = 192 kHz ÷4 ÷3 ÷2 49.152 36.864 24.567 49.152 49.152 49.152 256 192 128 256 256 256 CS5364 - - - - - - - - - - ÷1.5 ÷1 18.384 12.288 24.576 24.576 192 128 256 256 - - - - - - - - - - ÷1.5 ÷1 18.384 12 ...
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... RST pin low for a minimum of one MCLK cycle and then restoring the pin to a logic-high condition. 4.8.1 Power-Down Mode The CS5364 features a Power-Down Mode in which power is temporarily withheld from the modulators, the crystal oscillator driver, the digital core, and the serial port. The user can access Power-Down Mode by holding the device in reset and holding all clock lines at a static, valid logic level (either logic-high or logic- low) ...
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... COG capacitors are recommended for this application. For additional configurations, refer to Cirrus Application Note AN241 AIN+ 100kΩ AIN- 100kΩ 28 634 Ω 470 pF COG 91 Ω Ω Ω 91 Ω 470 pF COG 634 Ω Figure 15. Recommended Analog Input Buffer CS5364 ADC AIN+ COG 2700 pF ADC AIN- DS625F3 ...
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... DC Offset Control The CS5364 includes a dedicated high-pass filter for each channel to remove input DC offset at the system level level may result in audible “clicks” when switching between devices in a multi-channel system. In Stand-Alone Mode, all of the high-pass filters remain enabled. In Control Port Mode, the high-pass filters default to enabled, but may be controlled by writing to the HPF register ...
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... SPI Mode In SPI Mode the CS5364 chip select signal; CCLK is the control port bit clock (input into the CS5364 from a controller); CDIN is the input data line from a controller; CDOUT is the output data line to a controller. ...
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... SDA while SCL is high. All other transitions of SDA occur while SCL is low. The first byte sent to the CS5364 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper five bits of the 7-bit address field are fixed at 10011. To communicate with a CS5364, the chip address field, which is the first byte sent to the CS5364, should match 10011 and be followed by the settings of the AD1 and AD0 ...
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... Default: See description The Chip ID Code & Revision Register is used to store the ID and revision of the chip. Bits[7:4] contain the chip ID, where the CS5364 is represented with a value of 0x4. Bits[3:0] contain the revision of the chip, where revision A is represented as 0x0, revision B is represented as 0x1, etc ...
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... OVFL pin. When a particular bit is set low in the Mask register, the corresponding overflow bit in the Overflow Status register is prevented from causing any activity on the OVFL pin. DS625F3 DESCRIPTION Divide-by-1 Divide-by-1.5 Divide-by-2 Divide-by-3 Divide-by-4 Reserved OVFL4 OVFM4 CS5364 OVFL3 OVFL2 OVFL1 OVFM3 OVFM2 OVFM1 33 ...
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... When a bit is set, that channel’s serial data is muted by forcing the output to all zeroes HPF4 PDN-BG PDN-OSC RESERVED RESERVED MUTE4 CS5364 HPF3 HPF2 HPF1 “DC Offset Control” PDN43 PDN21 ...
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... RESERVED Default: 0x00, all SDOUT pins enabled. The SDOUT Enable Control Register is used to tri-state the serial audio data output pins. Each bit, when set, tri-states the associated SDOUT pin. DS625F3 RESERVED RESERVED CS5364 SDEN2 SDEN1 35 ...
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... FILTER PLOTS 0.1 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.1 0 0.05 0.1 0.1 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.1 0 0.05 0.1 0.1 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.1 0 0.05 36 0.15 0.2 0.25 0.3 Frequency (normalized to Fs) Figure 19. SSM Passband 0.15 0.2 0.25 0.3 Frequency (normalized to Fs) Figure 20. DSM Passband 0.1 0.15 Frequency (normalized to Fs) Figure 21. QSM Passband CS5364 0.35 0.4 0.45 0.5 0.35 0.4 0.45 0.5 0.2 0.25 DS625F3 ...
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... DS625F3 0.3 0.4 0.5 0.6 Frequency (normalized to Fs) Figure 22. SSM Stopband 0.3 0.4 0.5 0.6 Frequency (normalized to Fs) Figure 23. DSM Stopband 0.3 0.4 0.5 0.6 Frequency (normalized to Fs) Figure 24. QSM Stopband CS5364 0.7 0.8 0.9 1 0.7 0.8 0.9 1 0.7 0.8 0 ...
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... Frequency (normalized to Fs) Figure 25. SSM -1 dB Cutoff 0.46 0.48 0.5 0.52 Frequency (normalized to Fs) Figure 26. DSM -1 dB Cutoff 0.26 0.28 0.3 0.32 Frequency (normalized to Fs) Figure 27. QSM -1 dB Cutoff CS5364 0.54 0.56 0.58 0.6 0.54 0.56 0.58 0.6 0.34 0.36 0.38 0.4 DS625F3 ...
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... The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. Intrachannel Phase Deviation The deviation from linear phase within a given channel. Interchannel Phase Deviation The difference in phase response between channels. DS625F3 CS5364 39 ...
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... B B ∝ ∝ INCHES NOM MAX 0.055 0.063 0.004 0.006 0.009 0.011 0.354 0.366 0.28 0.280 0.354 0.366 0.28 0.280 0.020 0.024 0.24 0.030 4° 7.000° Symbol θ JA θ JC CS5364 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.22 0.27 8.70 9.0 BSC 9.30 6.90 7.0 BSC 7.10 8.70 9.0 BSC 9.30 6.90 7.0 BSC 7.10 0.40 0.50 BSC 0.60 0.45 0.60 0.75 0.00° ...
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... Package 114 dB, 192 kHz, 48-pin CS5364 4-channel A/D LQFP Converter CDB5364 Evaluation Board for CS5364 10.REVISION HISTORY Revision Updated the wording of pin 24, LRCK/FS, in the pin description table on page 7 to correctly reflect the F2 high/low clocking state for odd-channel selection in I²S and LJ Modes. F3 ...