adc1225ccd-1 National Semiconductor Corporation, adc1225ccd-1 Datasheet - Page 10

• Manufacturer Part Number: adc1225ccd-1
• Description: 12-bit Plus Sign Mp Compatible A/d Converters
• Manufacturer: National Semiconductor Corporation

Functional Description
3 0 INTERFACE
3 1 RESET OF INTERRUPT
INT goes low at the end of the conversion and indicates that
data is transferred to the output latch By reading data INT
will be reset to high on the leading edge of the first read (RD
going low) INT is also reset on the leading (falling) edge of
WR when starting a conversion
3 2 READY OUT
To simplify the hardware connection to high speed micro-
processors a READY OUT line is provided This allows the
A-to-D to insert a wait state in the mP’s read cycle The
equivalent circuit and the timing diagram for READY OUT is
shown in Figures 7 and 8
Location
Status
DB1
DB0
Bit
TABLE II Status Bit Locations and Meanings
FIGURE 7 READY OUT Equivalent Circuit
Status
EOC
INT
Bit
completed and data is
‘‘High’’ indicates that
‘‘High’’ indicates that
data is ready to read
conversion and the
it is the end of the
transferred to the
(Continued)
the conversion is
output latch
Meaning
(Continued)
Condition to
Clear Status
Data read or
status read
or status
TL H 5676 – 9
write
Bit
FIGURE 9
10
3 3 RESETTING THE A D
All the internal logic can be reset which will abort any con-
version in process and reset the status bits The reset func-
tion is achieved by performing a status write (CS WR and
STATUS are low)
3 4 ADDITIONAL TIMING AND INTERFACE OPTIONS
ADC1225
1 WR and RD can be tied together with CS low continu-
ously or strobed The previous conversion’s data will be
available when the WR and RD are low as shown below
One drawback is that since the conversion is started on the
falling edge and the data read on the rising edge of WR RD
the first data access will have erroneous information de-
pending on the power-up state of the internal output latch-
es
If the WR RD strobe is longer than the conversion time
INTR will never go low to signal the end of a conversion
The conversion will be completed and the output latches will
be updated In this case the READY OUT signal can be
used to sense the end of the conversion since it will go low
when the output latches are being updated
FIGURE 8 READY OUT Timing Diagram
TL H 5676 – 10
TL H 5676 – 24