ad1848 Analog Devices, Inc., ad1848 Datasheet
ad1848
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ad1848 Summary of contents
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... PRODUCT OVERVIEW The Parallel-Port AD1848K SoundPort® Stereo Codec inte- grates the key audio data conversion and control functions into a single integrated circuit. The AD1848K is intended to provide a complete, single-chip audio solution for business audio and multimedia applications requiring operation from a single +5 V SoundPort is a registered trademark of Analog Devices, Inc ...
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... AD1848K–SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature 25 Digital Supply (V ) 5.0 DD Analog Supply (V ) 5.0 CC Word Rate ( Input Signal 1008 Analog Output Passband kHz ADC FFT Size 2048 DAC FFT Size 8192 0.4 OL ANALOG INPUT ...
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... Specifications subject to change without notice. REV. 0 Min Max 0 0. 0.1 0. 30/F S 0.0 Min Typ –77 Min Typ –76 –3– AD1848K Units Max Units Bits dB 0.022 % – –80 dB –80 dB –80 dB – 0 LSBs Max Units Bits dB 0 ...
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... AD1848K DAC ATTENUATOR Step Size ( –34.5 dB) Step Size (– –94.5 dB)* Output Attenuation Range Span* ANALOG OUTPUT Full-Scale Output Voltage Output Impedance External Load Impedance Output Capacitance External Load Capacitance V REF V Current Drive REF V Output Impedance REF Mute Attenuation ...
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... Max Units 110 ns 110 Min Max Units 4.75 5.25 V 4.75 5.25 V 120 600 Min Max Units 27 MHz AD1848K S ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1848K features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... For DMA cycles, DBEN = (WR or RD) and (PDAK or CDAK) Data Bus Direction. This pin controls the direction of the data bus transceiver. HI enables writes from the host to the AD1848K; LO enables reads from the AD1848K to the host bus. This signal is normally HI. For control register/PIO cycles, ...
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... Host Interrupt Pin. This signal is used to notify the host that the DMA Current Count Register has underflowed. O External Control. These signals reflect the current status of register bits inside the AD1848K. They can be used for signaling or to control external logic. O Voltage Reference. Nominal 2.25 volt reference available for dc-coupling and level-shifting ...
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... The IORC post mixed DAC output is available on OUT externally and input to the ADCs. DATA7:0 Even if the AD1848K is not playing back data from its DACs, ISA BUS the analog mix function can still be active. A Analog-to-Digital Datapath DRQ<X> ...
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... The AD1848K operates from external crystals. Two crystal in- puts are provided to generate a wide range of sample rates. The oscillators for these crystals are on the AD1848K multi- plexer for selecting between them. They can be overdriven with external clocks by the user desired. The recommended crystal frequencies are 16 ...
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... UB7 UB6 15 LB7 LB6 Note that the only sticky bit in any of the AD1848K control registers is the interrupt (INT) bit. All other bits change with every sample period. REV. 0 Figure 5. AD1848K Indirect Register Map A detailed map of all direct and indirect register contents is ...
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... AD1848K Initialization. This bit is set when the AD1848K state which cannot respond to parallel bus cycles. This bit is read only. Immediately after reset and once the AD1848K has left the INIT state, the initial value of this register will be “0100 0000 (40h).” During AD1848K initialization, this register cannot be written and is always read “1000 0000 (80h).” ...
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... The IEN bit of the Pin Control Register determines whether the state of this bit is reflected on the INT pin of the AD1848K. The only interrupt condition supported by the AD1848K is generated by the underflow of the DMA Current Count Register. ...
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... The PIO Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register (PD7:0). Reads will receive data from the PIO Capture Data Register (CD7:0). During AD1848K initialization, the PIO Playback Data Register cannot be written and the Capture Data Register is always read “1000 0000 (80h).” ...
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... This register’s initial state after reset is “1000 0000 (80h).” REV. 0 Data 5 Data 4 Data 3 RMGE res RIG3 Data 5 Data 4 Data 3 res LX1A4 LX1A3 Data 5 Data 4 Data 3 res RX1A4 RX1A3 –15– AD1848K Data 2 Data 1 Data 0 RIG2 RIG1 RIG0 Data 2 Data 1 Data 0 LX1A2 LX1A1 LX1A0 Data 2 Data 1 Data 0 RX1A2 RX1A1 RX1A0 ...
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... AD1848K Left Auxiliary #2 Input Control (IXA3 IXA3:0 Data 7 Data 6 4 LMX2 res LX2A4:0 Left Auxiliary Input #2 Attenuate Select. The least significant bit of this gain/attenuate select represents –1.5 dB. LX2A4 produces a +12 dB gain. LX2A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is –34.5 dB. ...
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... FMT The contents of the Clock and Data Format Register cannot be changed except when the AD1848K is in Mode Change Enable (MCE) state. Write attempts to this register when the AD1848K is not in the MCE state will not be successful. CSS Clock Source Select. This bit selects the crystal clock source which will be used for the audio sample rate. ...
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... The contents of the Interface Configuration Register cannot be changed except when the AD1848K is in Mode Change Enable (MCE) state. Write attempts to this register when the AD1848K is not in the MCE state will not be successful. PEN and CEN are exceptions; these bits may always be written. ...
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... Reserved for future expansion. The bits are read only. Do not write to these bits. ID3:0 AD1848K Revision ID. These four bits define the revision level of the AD1848K. Revisions increment by one LSB. The K-Grade revision “1010.” These bits are read only. This register’s initial state after reset is “xxxx RRRR” where RRRR = Revision ID of the silicon in use. ...
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... DMA Base Count Registers (IXA3 & 15) The DMA Base Count Registers in the AD1848K simplify integration of the AD1848K in ISA systems. The ISA DMA controller re- quires an external count mechanism to notify the host CPU via interrupt of a full DMA buffer. The programmable DMA Base Count Registers will allow such interrupts to occur ...
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... DMA. Transfers to and from the AD1848K SoundPort Codec are asynchronous relative to the internal data conversion clock. Transfers are buffered, but the AD1848K supports no in- ternal FIFOs. The host is responsible for providing playback data before the next digital-to-analog conversion and removing capture data before the next analog-to-digital conversion ...
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... Because their change is referenced to the internal sample clock, no useful timing diagram can be constructed. Direct Memory Access (DMA) Transfers The second type of bus cycle supported by the AD1848K are DMA transfers. Both dual channel and single channel DMA op- erations are supported. To enable Playback DMA transfers, playback enable (PEN) must be set and PPIO cleared ...
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... Figure 13. AD1848K 8-Bit Mono DMA Read/Capture Cycle ISA BUS BCLK CDRQ/ PDRQ OUTPUTS CDAK/ PDAK INPUTS INPUTS DATA7:0 Figure 15. AD1848K 8-Bit Stereo or 16-Bit Mono DMA Cycle ISA BUS BCLK CDRQ/ PDRQ OUTPUTS CDAK/ PDAK INPUTS INPUTS DATA7:0 REV. 0 ISA BUS ...
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... V prior to system autocalibration. At any point when powered, the AD1848K can be put into a state for minimum power consump- tion by asserting PWRDWN LO. All analog and digital sections are shut down. The AD1848K’s parallel interface does not func- tion ...
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... The AD1848K SoundPort only powered device. Line level voltage swings for the AD1848K are defined rms for a sine wave ADC input and 0.707 V rms for a sine wave DAC output. Thus rms ...
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... The digital ground and analog grounds should be tied together in the vicinity of the AD1848K. Other schemes may also yield satisfactory results. If the split ground plane recom- mended here is not possible, the AD1848K should be entirely over the analog ground plane with the 74_245 transceiver over the digital plane. ...
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... S Figure 28. AD1848K Digital-to-Analog Frequency Response (Full-Scale Inputs Attenuation –10 –20 –30 –40 –50 dB –60 –70 –80 –90 –100 –110 –120 0.54 0.56 0.58 0.60 0. Figure 29. AD1848K Digital-to-Analog Frequency Response—Transition Band (Full-Scale Inputs Attenuation) –27– AD1848K 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 SAMPLE FREQUENCY ( 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 ...
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... AD1848K P-68A 68-Lead Plastic Leaded Chip Carrier 0.175 (4.45) 0.995 (25.27) 0.169 (4.29) SQ 0.885 (22.48 PIN 1 IDENTIFIER TOP VIEW 0.954 (24.23) SQ 0.104 (2.64) TYP 0.950 (24.13) INDEX PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . 2 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PINOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AUDIO FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . 9 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Analog Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Analog-to-Digital Datapath . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital-to-Analog Datapath ...