adsp-2188m Analog Devices, Inc., adsp-2188m Datasheet - Page 13

• Manufacturer Part Number: adsp-2188m
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

DMOVLAY
0, 4, 5, 6, 7, 8
1
2
Data Memory
Data Memory (Full Memory Mode) is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The ADSP-2188M has 56K words on Data
Memory RAM on-chip. Part of this space is used by 32 memory-
mapped registers. Support also exists for up to two 8K external
memory overlay spaces through the external data bus. All internal
accesses complete in one cycle. Accesses to external memory are
timed using the wait states specified by the DWAIT register and
the wait state mode bit.
Data Memory (Host Mode) allows access to all internal memory.
External overlay access is limited by a single external address
line (A0).
Memory Mapped Registers (New to the ADSP-2188M)
The ADSP-2188M has three memory mapped registers that differ
from other ADSP-21xx Family DSPs. The slight modifications
to these registers (Wait State Control, Programmable Flag and
Composite Select Control, and System Control) provide the
ADSP-2188M’s wait state and BMS control features. Default
bit values at reset are shown; if no value is shown, the bit is unde-
fined at reset. Reserved bits are shown on a grey field. These bits
should always be written with zeros.
WAIT STATE MODE SELECT
0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES, RANGING
1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, RANGING
FROM 0 TO 7)
FROM 0 TO 15)
15 14 13 12 11 10 9
1
1
DWAIT
1
1
1
IOWAIT3
WAITSTATE CONTROL
1
Memory
Internal
External Overlay 1
External Overlay 2
1
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
ACCESSIBLE WHEN
DMOVLAY = 0
8
1
DATA MEMORY
IOWAIT2
INTERNAL
MEMORY
ACCESSIBLE WHEN
DMOVLAY = 4
7
1
6
1
ACCESSIBLE WHEN
DMOVLAY = 5
5
1
IOWAIT1
ACCESSIBLE WHEN
DMOVLAY = 6
4
1
3
1
ACCESSIBLE WHEN
DMOVLAY = 7
0x0000 – 0x1FFF
2
1
IOWAIT0
EXTERNAL
ACCESSIBLE WHEN
DMOVLAY = 8
MEMORY
1
1
0x0000 – 0x1FFF
0
1
ACCESSIBLE WHEN
DMOVLAY = 1
0x0000 – 0x1FFF
DM(0x3FFE)
Table IV. DMOVLAY Bits
A13
Not Applicable
0
1
ACCESSIBLE WHEN
DMOVLAY = 2
0x0000 – 0x1FFF
0x0000 – 0x1FFF
0x0000 – 0x1FFF
0 x 0000 –0 x 1FFF
SPORT0 ENABLE
0 = DISABLE
1 = ENABLE
NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD
SPORT1 CONFIGURE
0 = FI, FO, IRQ0, IRQ1, SCLK
1 = SPORT1
RESERVED
15 14 13 12 11 10 9
0
SET TO 0
SPORT1 ENABLE
0 = DISABLE
1 = ENABLE
15 14 13 12 11 10 9
1
BMWAIT
0 x 0000 –0 x 1FFF
0
ALWAYS BE WRITTEN WITH ZEROS.
1
0
1
AND COMPOSITE SELECT CONTROL
0
DMOVLAY = 0, 4, 5, 6, 7, 8
A12:0
Not Applicable
13 LSBs of Address Between 0x2000 and 0x3FFF
13 LSBs of Address Between 0x2000 and 0x3FFF
1
(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)
0
DMOVLAY = 1, 2
DATA MEMORY
1
PROGRAMMABLE FLAG
8K EXTERNAL
8K INTERNAL
8160 WORDS
32 MEMORY
REGISTERS
SYSTEM CONTROL
INTERNAL
1
MAPPED
CMSSEL
0 = DISABLE CMS
1 = ENABLE CMS
0
OR
RESERVED, ALWAYS
0
1
8
0
8
1
SET TO 0
7
0
7
0
DISABLE BMS
0 = ENABLE BMS
1 = DISABLE BMS, EXCEPT WHEN MEMORY
6
0
6
0
STROBES ARE THREE-STATED
5
0
ADDRESS
5
0
0 x 3FFF
0 x 3FE0
0 x 3FDF
0 x 1FFF
0 x 2000
0 x 0000
PFTYPE
0 = INPUT
1 = OUTPUT
4
0
4
0
3
0
ADSP-2188M
3
0
PWAIT
PROGRAM MEMORY
WAIT STATES
2
1
2
0
1
1
1
0
0
1
0
0
DM(0x3FFF)
DM(0x3FE6)