adsp-2188m Analog Devices, Inc., adsp-2188m Datasheet - Page 26

• Manufacturer Part Number: adsp-2188m
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-2188M
Parameter
Bus Request–Bus Grant
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
2
BH
BS
SD
SDB
SE
SEC
SDBH
SEH
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
BR Hold after CLKOUT High
BR Setup before CLKOUT Low
CLKOUT High to xMS, RD, WR Disable
xMS, RD, WR Disable to BG Low
BG High to xMS, RD, WR Enable
xMS, RD, WR Enable to CLKOUT High
xMS, RD, WR Disable to BGH Low
BGH High to xMS, RD, WR Enable
PMS, DMS
BMS, RD
CLKOUT
CLKOUT
BGH
WR
BG
BR
t
SD
t
1
BH
1
t
t
BS
t
SDBH
SDB
2
2
Min
0.25t
0.25t
0
0
0.25t
0
0
t
t
SEH
SE
CK
CK
CK
t
+ 2
+ 10
– 3
SEC
Max
0.25t
CK
+ 8
Unit
ns
ns
ns
ns
ns
ns
ns
ns