adsp-2188m Analog Devices, Inc., adsp-2188m Datasheet - Page 16

• Manufacturer Part Number: adsp-2188m
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

Bootstrap Loading (Booting)
The ADSP-2188M has two mechanisms to allow automatic load-
ing of the internal program memory after reset. The method for
booting is controlled by the Mode A, B, and C configuration bits.
When the MODE pins specify BDMA booting, the ADSP-2188M
initiates a BDMA boot sequence when reset is released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD, and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of
on-chip program memory to be loaded from byte memory.
These 32 words are used to set up the BDMA to load in the
remaining program code. The BCR bit is also set to 1, which
causes program execution to be held off until all 32 words are
loaded into on-chip program memory. Execution then begins at
address 0.
The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.
The IDLE instruction can also be used to allow the processor
to hold off execution while booting continues through the
BDMA interface. For BDMA accesses while in Host Mode, the
addresses to boot memory must be constructed externally to the
ADSP-2188M. The only memory address bit provided by the
processor is A0.
IDMA Port Booting
The ADSP-2188M can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the
ADSP-2188M boots from the IDMA port. IDMA feature can
load as much on-chip memory as desired. Program execution is
held off until on-chip program memory location 0 is written to.
ADSP-2188M
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF
ACCESSIBLE WHEN
PMOVLAY = 0
NOTE: IDMA AND BDMA HAVE SEPARATE DMA CONTROL REGISTERS.
PROGRAM MEMORY
ACCESSIBLE WHEN
PMOVLAY = 4
OVLAY
DMA
ACCESSIBLE WHEN
PMOVLAY = 5
ACCESSIBLE WHEN
PMOVLAY = 6
ACCESSIBLE WHEN
PMOVLAY = 7
0x2000 – 0x3FFF
0x2000 – 0x3FFF
0x2000 – 0x3FFF
0x2000 – 0x3FFF
0x2000 – 0x3FFF
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
ACCESSIBLE WHEN
DMOVLAY = 0
DATA MEMORY
Bus Request and Bus Grant
The ADSP-2188M can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
ADSP-2188M is not performing an external memory access, it
responds to the active BR input in the following processor cycle by:
• Three-stating the data and address buses and the PMS, DMS,
• Asserting the bus grant (BG) signal, and
• Halting program execution.
If Go Mode is enabled, the ADSP-2188M will not halt program
execution until it encounters an instruction that requires an
external memory access.
If the ADSP-2188M is performing an external memory access
when the external device asserts the BR signal, it will not three-
state the memory interfaces nor assert the BG signal until the
processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single
instruction requires two external memory accesses, the bus will
be granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers, and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The BGH pin is asserted when the ADSP-2188M requires the
external bus for a memory or BDMA access, but is stopped.
The other device can release the bus by deasserting bus request.
Once the bus is released, the ADSP-2188M deasserts BG and
BGH and executes the external memory access.
Flag I/O Pins
The ADSP-2188M has eight general purpose programmable
input/output flag pins. They are controlled by two memory
mapped registers. The PFTYPE register determines the direc-
tion, 1 = output and 0 = input. The PFDATA register is used to
read and write the values on the pins. Data being read from a
pin configured as an input is synchronized to the ADSP-2188M’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
ACCESSIBLE WHEN
DMOVLAY = 4
BMS, CMS, IOMS, RD, WR output drivers,
OVLAY
DMA
ACCESSIBLE WHEN
DMOVLAY = 5
ACCESSIBLE WHEN
DMOVLAY = 6
ACCESSIBLE WHEN
DMOVLAY = 7
0x0000 – 0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 8
0x0000 – 0x1FFF
0x0000 – 0x1FFF
0x0000 – 0x1FFF
0x0000 – 0x1FFF
0x0000 – 0x1FFF