adsp-21364bbc Analog Devices, Inc., adsp-21364bbc Datasheet - Page 7

• Manufacturer Part Number: adsp-21364bbc
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Table 3. ADSP-2136x Internal Memory Space
The DAI also includes six serial ports, an S/PDIF receiver/trans-
mitter, a DTCP cipher, a precision clock generator (PCG), eight
channels of asynchronous sample rate converters, an input data
port (IDP), an SPI port, six flag outputs and six flag inputs, and
three timers. The IDP provides an additional input path to the
ADSP-2136x core, configurable as either eight channels of I
serial data or as seven channels plus a single 20-bit wide syn-
chronous parallel data acquisition port. Each data channel has
its own DMA channel that is independent from the processor’s
serial ports.
For complete information on using the DAI, see the
ADSP-2136x SHARC Processor Hardware Reference.
Serial Ports
The ADSP-2136x features six synchronous serial ports that pro-
vide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and a frame sync.
The data lines can be programmed to either transmit or receive
and each data line has a dedicated DMA channel.
Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
receive channels of audio data when all six SPORTS are enabled,
or six full duplex TDM streams of 128 channels per frame.
IOP Registers 0x0000 0000–0003 FFFF
Long Word (64 Bits)
Block 0 ROM
0x0004 0000–0x0004 7FFF
Reserved
0x0004 8000–0x0004 BFFF
Block 0 SRAM
0x0004 C000–0x0004 FFFF
Block 1 ROM
0x0005 0000–0x0005 7FFF
Reserved
0x0005 8000–0x0005 BFFF
Block 1 SRAM
0x0005 C000–0x0005 FFFF
Block 2 SRAM
0x0006 0000–0x0006 1FFF
Reserved
0x0006 2000–0x0006 FFFF
Block 3 SRAM
0x0007 0000–0x0007 1FFF
Reserved
0x0007 2000–0x0007 FFFF
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Extended Precision Normal or
Instruction Word (48 Bits)
Block 0 ROM
0x0008 0000–0x0008 AAA9
Block 0 SRAM
0x0009 0000–0x0009 5554
Block 1 ROM
0x000A 0000–0x000A AAA9
Block 1 SRAM
0x000B 0000–0x000B 5554
Block 2 SRAM
0x000C 0000–0x000C 2AA9
Block 3 SRAM
0x000E 0000–0x000E 2AA9
Rev. D | Page 7 of 56 | April 2008
2
S
Normal Word (32 Bits)
Block 0 ROM
0x0008 0000–0x0008 FFFF
Reserved
0x0009 0000–0x0009 7FFF
Block 0 SRAM
0x0009 8000–0x0009 FFFF
Block 1 ROM
0x000A 0000–0x000A FFFF
Reserved
0x000B 0000–0x000B 7FFF
Block 1 SRAM
0x000B 8000–0x000B FFFF
Block 2 SRAM
0x000C 0000–0x000C 3FFF
Reserved
0x000C 4000–0x000D FFFF
Block 3 SRAM
0x000E 0000–0x000E 3FFF
Reserved
0x000E 4000–0x000F FFFF
The serial ports operate at a maximum data rate of 41.67 Mbps.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig-
nals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
Serial ports operate in four modes:
Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var-
ious attributes of this mode.
Each of the serial ports supports the left-justified sample pair
and I
monly used by audio codecs, ADCs, and DACs, such as the
Analog Devices AD183x family), with two data pins, allowing
four left-justified sample pairs or I
devices) per serial port, with a maximum of up to 24 I
• Standard DSP serial mode
• Multichannel (TDM) mode
• I
• Left-justified sample pair mode
2
2
S protocols (I
S mode
2
S is an industry-standard interface com-
Short Word (16 Bits)
Block 0 ROM
0x0010 0000–0x0011 FFFF
Reserved
0x0012 0000–0x0012 FFFF
Block 0 SRAM
0x0013 0000–0x0013 FFFF
Block 1 ROM
0x0014 0000–0x0015 FFFF
Reserved
0x0016 0000–0x0016 FFFF
Block 1 SRAM
0x0017 0000–0x0017 FFFF
Block 2 SRAM
0x0018 0000–0x0018 7FFF
Reserved
0x0018 8000–0x001B FFFF
Block 3 SRAM
0x001C 0000–0x001C 7FFF
Reserved
0x001C 8000–0x001F FFFF
Reserved
0x0020 0000–0xFFFF FFFF
2
S channels (using two stereo
2
S