dsp56367 Freescale Semiconductor, Inc, dsp56367 Datasheet
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dsp56367 Summary of contents
Page 1
... This document briefly describes the DSP56367 24-bit digital signal processor (DSP). The DSP56367 is a member of the DSP56300 family of programmable CMOS DSPs. The DSP56367 is targeted to applications that require digital audio compression/decompression, sound field processing, acoustic equalization and other digital audio algorithms. The DSP56367 offers 150 million instructions per second (MIPS) using an internal 150 MHz clock at 1 ...
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... DSP56300 Core DDB YDB XDB PDB GDB PROGRAM PROGRAM DECODE ADDRESS TWO 56-BIT ACCUMULATORS CONTROLLE GENERATOR MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD Figure 1-1 DSP56367 Block Diagram DSP56367 Technical Data, Rev. 2.1 Signal State Voltage* Asserted Deasserted Asserted Deasserted ...
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... Off-chip expansion up to 16M x 24-bit word of Program memory. • Simultaneous glueless interface to SRAM and DRAM. 1.5 Peripheral modules • Serial Audio Interface (ESAI receivers and transmitters, master or slave. I AC97, network and other programmable protocols. Freescale Semiconductor i : i=0 to 7). Reduces clock noise. DSP56367 Technical Data, Rev. 2.1 Overview 2 S, Sony, 1-3 ...
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... Documentation Table 1-1 lists the documents that provide a complete description of the DSP56367 and are required to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, a Freescale Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source for the latest information). ...
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... Table 2-1 and illustrated in Figure The DSP56367 is operated from a 1.8V supply; however, some of the inputs can tolerate 3.3V. A special notice for this feature is added to the signal descriptions of those inputs. Remember, the DSP56367 offers 150 million instructions per second (MIPS) using an internal 150 MHz clock at 1.8 V and 100 million instructions per second (MIPS) using an internal 100 MHz clock at 1.3.3V. ...
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... OnCE‰ ON-CHIP EMULATION/ DSP56367 PARALLEL HOST PORT (HDI08) Port B SERIAL AUDIO INTERFACE (ESAI) Port C SERIAL AUDIO INTERFACE(ESAI_1) Port E Port D SERIAL HOST INTERFACE (SHI) DSP56367 Technical Data, Rev. 2.1 JTAG PORT TDI TCK TDO TMS HAD(7:0) [PB0-PB7] HAS/HA0 [PB8] HA8/HA1 [PB9] HA9/HA2 [PB10] ...
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... I/O drivers. This A connections isolated ground for sections of the data bus I/O drivers. This connection D connections. D DSP56367 Technical Data, Rev. 2.1 power rail. There is one V input. CC CCP power pin only. Do not tie with other power pins. inputs. CCQL by a 0.47 µ ...
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... Input PINIT/NMI Input Input 2.5 External Memory Expansion Port (Port A) When the DSP56367 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0–AA2/RAS2, RD, WR, BB, CAS. 2.6 External Address Bus State During Signal Name Type Reset A0– ...
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... TA can operate synchronously or asynchronously, depending on the setting of the TAS bit in the operating mode register (OMR). TA functionality may not be used while performing DRAM type accesses, otherwise improper operation may result. DSP56367 Technical Data, Rev. 2.1 External Data Bus Signal Description 2-5 ...
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... BR may be asserted or deasserted independent of whether the DSP56367 is a bus master or a bus slave. Bus “parking” allows deasserted even though the DSP56367 is the bus master. (See the description of bus “parking” in the BB signal description.) The bus request hold (BRH) bit in the BCR allows asserted under software control even though the DSP does not need the bus ...
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... When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET is being asserted. This input is 3.3V tolerant. DSP56367 Technical Data, Rev. 2.1 Interrupt and Mode Control 2-7 ...
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... HI function is selected, this signal is line 8 of the host address (HA8) input bus. Port B 9—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant. DSP56367 Technical Data, Rev. 2.1 Signal Description Freescale Semiconductor ...
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... Port B 12—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant. DSP56367 Technical Data, Rev. 2.1 Parallel Host Interface (HDI08) Signal Description 2-9 ...
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... Port B 15—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant. DSP56367 Technical Data, Rev. 2.1 Signal Description Freescale Semiconductor ...
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... SCL is high is a unique situation defined as the stop event. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 3.3V tolerant. DSP56367 Technical Data, Rev. 2.1 Serial Host Interface 2 C bus transactions in the I ...
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... This signal is tri-stated during hardware, software, personal reset, or when the HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in this state. This input is 3.3V tolerant. DSP56367 Technical Data, Rev. 2 master mode Slave mode, the HA2 signal is used master mode ...
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... Port C 1—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. DSP56367 Technical Data, Rev. 2.1 Enhanced Serial Audio Interface 2-13 ...
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... RX0 serial receive shift register. Port C 6—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
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... Port C 10—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 10 signal. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. DSP56367 Technical Data, Rev. 2.1 Enhanced Serial Audio Interface 2-15 ...
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... ESAI transmit clock control register (TCCR). Port E 4—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 3.3V. DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
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... RX1 serial receive shift register. Port E 7—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. DSP56367 Technical Data, Rev. 2.1 Enhanced Serial Audio Interface_1 2-17 ...
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... If TIO0 is not being used recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected to Vcc through a pull-up resistor in order to ensure a stable logic level at this input. This input is 3.3 V tolerant. DSP56367 Technical Data, Rev. 2.1 Signal Description Signal Description Freescale Semiconductor ...
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... TDO changes on the falling edge of TCK. Test Mode Select—TMS is an input signal used to sequence the test controller’s state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 3.3V tolerant. DSP56367 Technical Data, Rev. 2.1 JTAG/OnCE Interface 2-19 ...
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... JTAG/OnCE Interface 2-20 NOTES DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
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... Specifications 3.1 Introduction The DSP56367 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs and outputs. This document contains information on a new product. Specifications and information herein are subject to change without notice. Finalized specifications may be published after further characterization and device qualifications are completed ...
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... CCD CCC, CCH, CCS and GND STG Table 3-2 Thermal Characteristics Symbol 1,2 R θ θJC 4 DSP56367 Technical Data, Rev. 2 Value − 0 2.0 − 0 4.0 − GND 0 0 − − +125 TQFP Value Unit or θ ° 45.0 C θ ...
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... ILP /SHI (only SDO4_1) (SPI mode) V ILP V ILX TSI CCI I CCW I CCS DSP56367 Technical Data, Rev. 2.1 DC Electrical Characteristics 1 Min Typ Max 1.71 1.8 1.89 3.14 3.3 3.46 2.0 — V CCQH 2.0 — max CCQH for both V IHP 1.5 — max CCQH ...
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... V for all pins except EXTAL. AC timing specifications, which are IH referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal’s transition. DSP56367 output levels are measured with the production test machine V and V reference levels set at 0.4 V and 2.4 V, respectively. ...
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... MF = Multiplication Factor PDF = Predivision Factor T = internal clock cycle C 2 DSP56300 Family Manual Refer to the 3.7 External Clock Operation The DSP56367 system clock is an externally supplied square wave voltage source connected to EXTAL(Figure 3-1). EXTAL V ILC Note: The midpoint is 0.5 (V No. Characteristics 1 Frequency of EXTAL (EXTAL Pin Frequency) The rise and fall time of this external clock should maximum ...
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... Table 3-5 Clock Operation (continued and maximum MF. CO and maximum DF. CO Table 3-6 PLL Characteristics Min × 2/PDF CCP PCAP (MF × 580) − 100 MF × 830 DSP56367 Technical Data, Rev. 2.1 Symbol Min Max ET C ∞ 6.7 ns 273.1 µs 6 CYC ∞ 13.33 ns 8.53 µs 6.67 ns Max Unit ...
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... Expression 2 50 × ET 1000 × ET 75000 × ET 75000 × ET 2.5 × T 2.5 × 3.25 × 2.0 20.25 × 3.25 × T 20.25 × T 4.25 × T 7.25 × × T (WS + 3.75) × T (WS + 3.25) × T DSP56367 Technical Data, Rev. 2.1 1 Min Max Unit — — 26.0 333.4 — C 6.7 — C 500 — C 500 — ...
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... PLC/2) × T PLC × +/- 0.5) × T (8.25 ± 0.5) × T PLC × ET × PDF + (128 K C − PLC/2) × T PLC × +/- 0.5) × T 5.5 × T 12T 12T DSP56367 Technical Data, Rev. 2.1 1 (continued) Min Max Unit – 10.94 — Note 8 C N/A — Note 8 – 4.0 — ...
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... Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing Expression 4.25 × –40° 95° and T will not be constant, and their width may vary DSP56367 Technical Data, Rev. 2.1 1 (continued) Min Max Unit 6T — 40 — — ...
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... NMI General Purpose I/O IRQA, IRQB, IRQC, IRQD, NMI 3-10 9 Reset Value Figure 3-2 Reset Timing First Interrupt Instruction Execution/Fetch First Interrupt Instruction Execution 18 b) General Purpose I/O Figure 3-3 External Fast Interrupt Timing DSP56367 Technical Data, Rev. 2 First Fetch AA0460 Freescale Semiconductor ...
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... A0–A17 Figure 3-6 Recovery from Stop State Using IRQA Interrupt Service Freescale Semiconductor Figure 3-5 Operating Mode Select Timing 24 25 DSP56367 Technical Data, Rev. 2.1 Reset, Stop, Mode Select, and Interrupt Timing AA0463 IRQA, IRQB IRQD, NMI V IL AA0465 ...
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... × T 0.75 × 1.25 × × (WS − 0.5) × T 1.25 × 2.25 × T DSP56367 Technical Data, Rev. 2.1 First IRQA Interrupt Instruction Fetch AA0467 AA1104 150 MHz 1 Expression Min Max − 4.0 [2 ≤ WS ≤ 7] 22.7 — C − 4.0 [WS ≥ 8] 69.3 — C − 2.0[2 ≤ WS ≤ 3] 3.0 — ...
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... T 2.25 × T 1.25 × T — 2.25 × T 3.25 × T 1.75 × T 2.75 × T 2.0 × T 2.5 × T 3.5 × T (WS + 0.25) × T 1.25 × T 2.25 × 0.25 × T DSP56367 Technical Data, Rev. 2.1 External Memory Expansion Port (Port A) 150 MHz 1 Expression Min Max − 5.0 [WS ≥ 2] — 13.3 C − 5.0 [WS ≥ 2] — 10.0 C 0.0 — − 4.0 [WS ≥ 2] 14.3 — ...
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... D0–D23 3-14 100 113 116 115 105 104 119 Figure 3-9 SRAM Read Access 100 107 101 102 114 108 Figure 3-10 SRAM Write Access DSP56367 Technical Data, Rev. 2.1 117 106 118 Data In AA0468 103 118 119 109 Data Out Freescale Semiconductor ...
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... Note: This figure should be use for primary selection. For exact and detailed timings see the following tables. 120 66 80 100 3 Wait States 4 Wait States DSP56367 Technical Data, Rev. 2.1 External Memory Expansion Port (Port A) Chip Frequency (MHz) AA0472 3-15 ...
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... CRP ASC t CAH t RAL t RCS t RCH t WCH RWL t CWL WCS t ROH DSP56367 Technical Data, Rev. 2 100 MHz 4 Expression Unit Min Max 2 × T 20.0 — 1.25 × T 12.5 — × T − 7.0 — 13 × T − 7.0 — 23 0.0 — ...
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... The number of wait states for Page mode access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 The asynchronous delays specified in the expressions are valid for DSP56367. 4 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t read-after-read or write-after-write sequences). ...
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... The number of wait states for Page mode access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 The asynchronous delays specified in the expressions are valid for DSP56367. 4 All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example × T for read-after-read or write-after-write sequences) ...
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... Column Column Address Address 151 144 145 146 155 150 149 Data Out Data Out DSP56367 Technical Data, Rev. 2.1 External Memory Expansion Port (Port A) 136 135 138 142 Last Column Address 143 147 148 156 Data Out AA0473 3-19 ...
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... RD D0–D23 Figure 3-13 DRAM Page Mode Read Accesses 3-20 131 137 139 140 141 Column Column Address Address 143 133 153 Data In Data In DSP56367 Technical Data, Rev. 2.1 136 135 138 142 Last Column Address 132 152 134 154 Data In AA0474 Freescale Semiconductor ...
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... T − 7 OFF 1.75 × 3.25 × RAS C 1.75 × RSH C DSP56367 Technical Data, Rev. 2.1 External Memory Expansion Port (Port A) Chip Frequency (MHz) AA0475 MHz 30 MHz Min Max Min Max 250.0 — 166.7 − 7.5 — 130.0 — ...
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... CWL C 2.25 × T − 4 1.75 × T − 4 3.25 × T − 4.0 t DHR C 3 × T − 4.3 t WCS C 0.5 × T − 4.0 t CSR C 1.25 × T − 4.0 t RPC C DSP56367 Technical Data, Rev. 2 (continued MHz 30 MHz Unit Min Max Min Max 133.5 — 87.7 — ns 58.5 — 37.7 — ns 73.0 77.0 48.0 52.0 ns 60.5 64.5 39.7 43.7 ns 108.5 — ...
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... AA t OFF RAS t RSH t CSH t CAS t RCD t RAD t CRP ASR t RAH DSP56367 Technical Data, Rev. 2.1 External Memory Expansion Port (Port (continued MHz 30 MHz Min Max Min Max 221.0 — 146.0 — — 192.5 — 125.8 0.0 — 0.0 — 37.2 — ...
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... WR deassertion to data high impedance 1 The number of wait states for out-of-page access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 The asynchronous delays specified in the expressions are valid for DSP56367. 4 Either must be satisfied for read cycles. RCH RRH 5 RD deassertion will always occur after CAS deassertion ...
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... T t RAL 5 × RCS 1.75 × RCH 0.25 × RRH 6 × WCH 9.5 × WCR 15.5 × DSP56367 Technical Data, Rev. 2.1 External Memory Expansion Port (Port 100 MHz 3 Min Max 160.0 — C − 5.7 — 76.8 C − 5.7 — 41.8 C − 5.7 — 49 ...
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... Symbol 15.75 × RWL 14.25 × CWL DHR t WCS t CSR t RPC t ROH DSP56367 Technical Data, Rev. 2 (continued) 100 MHz 3 Expression Min Max − 4.3 153.2 — C − 4.3 138.2 — C 8.75 × T − 4.0 83.5 — C 6.25 × T − 4.0 58.5 — C 9.75 × T − 4.0 93.5 — ...
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... Freescale Semiconductor 157 163 165 167 164 168 170 166 171 173 175 Row Address Column Address 172 176 177 191 160 159 158 192 DSP56367 Technical Data, Rev. 2.1 External Memory Expansion Port (Port A) 162 174 179 168 193 161 Data In AA0476 3-27 ...
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... Figure 3-16 DRAM Out-of-Page Write Access 3-28 157 163 165 167 164 168 166 170 171 173 172 176 Row Address Column Address 181 175 188 180 182 184 183 187 186 185 194 Data Out DSP56367 Technical Data, Rev. 2.1 162 174 195 AA0477 Freescale Semiconductor ...
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... Freescale Semiconductor 157 163 162 165 189 Figure 3-17 DRAM Refresh Access Expression 2 . Table 3-14 Figure 3-18 . DSP56367 Technical Data, Rev. 2.1 External Memory Expansion Port (Port A) 162 AA0478 150 MHz Unit Min Max — 21.7 18.3 — is required. ...
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... BG asserted, and BB negated, may cause another 56300 component to assume mastership at the same time. Therefore some non-overlap period between one BG input active to another BG input active is required. Timing 251 ensures that such a situation is avoided. 3-30 250 250+251 DSP56367 Technical Data, Rev. 2.1 251 Freescale Semiconductor ...
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... HCS assertion to write data strobe deassertion Freescale Semiconductor after “Last Data Register” reads DSP56367 Technical Data, Rev. 2.1 Parallel Host Interface (HDI08) Timing 150 MHz Expression Min Max T + 9.9 16.7 — C — 9.9 — 2.5 × 6.6 23.3 — C — 13.2 — ...
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... Delay from DMA HACK assertion to HOREQ deassertion for “Last Data Register” read or write • HROD = 1, open drain Host Request 1 See Host Port Usage Considerations in the DSP56367 User’s Manual the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable 1.8 V ± ...
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... HTRQ Figure 3-21 Read Timing Diagram, Non-Multiplexed Bus Freescale Semiconductor 317 327 329 326 336 337 330 317 318 328 332 319 327 329 326 340 341 DSP56367 Technical Data, Rev. 2.1 Parallel Host Interface (HDI08) Timing 318 328 AA1105 333 338 AA0484 3-33 ...
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... Parallel Host Interface (HDI08) Timing HA0–HA2 HCS HWR, HDS HD0–HD7 HOREQ, HRRQ, HTRQ Figure 3-22 Write Timing Diagram, Non-Multiplexed Bus 3-34 336 331 320 321 324 340 341 DSP56367 Technical Data, Rev. 2.1 337 333 325 339 AA0485 Freescale Semiconductor ...
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... HRD, HDS HAD0–HAD7 HOREQ, HRRQ, HTRQ Figure 3-23 Read Timing Diagram, Multiplexed Bus Freescale Semiconductor 336 337 323 317 334 335 327 328 329 Address Data 326 340 341 DSP56367 Technical Data, Rev. 2.1 Parallel Host Interface (HDI08) Timing 318 319 338 AA0486 3-35 ...
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... HACK (Input) H0–H7 (Input) Figure 3-25 Host DMA Write Timing Diagram 3-36 336 323 320 334 324 335 Data Address 340 341 342 343 344 320 321 TXH/M/L Write 324 325 Data Valid DSP56367 Technical Data, Rev. 2.1 321 325 339 AA0487 Freescale Semiconductor ...
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... Wide Master Bypassed Narrow Wide Slave Bypassed Narrow Wide Master Bypassed Narrow Wide Slave Bypassed Narrow Wide DSP56367 Technical Data, Rev. 2.1 Serial Host Interface SPI Protocol Timing 342 318 328 329 2 Expression Min Max — — — — 50 — — 100 6 × ...
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... Narrow Wide Master/ Bypassed Slave Narrow Wide Slave — Slave Bypassed 2.5 × T Narrow 2.5 × T Wide Slave Bypassed Narrow 2.5 × T Wide Slave — DSP56367 Technical Data, Rev. 2.1 2 Expression Min Max — — 10 — — 2000 3.5 × 38.5 — — — ...
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... Master — 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 163 Figure 3-27 SPI Master Timing (CPHA = 0) DSP56367 Technical Data, Rev. 2.1 Serial Host Interface SPI Protocol Timing 2 Expression Min 12.7 C 0.5 × 2.5 × 97.8 SPICC C 0.5 × 2.5 × 160 ...
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... MOSI (Output) 161 HREQ (Input) 3-40 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 162 163 Figure 3-28 SPI Master Timing (CPHA = 1) DSP56367 Technical Data, Rev. 2.1 141 144 141 144 148 149 LSB Valid 153 LSB AA0272 Freescale Semiconductor ...
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... MSB 149 MSB Valid 157 Figure 3-29 SPI Slave Timing (CPHA = 0) DSP56367 Technical Data, Rev. 2.1 Serial Host Interface SPI Protocol Timing 141 147 144 160 141 144 151 LSB 148 149 LSB Valid 159 ...
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... C Protocol Timing 2 Table 3-17 SHI I C Protocol Timing 2 Standard I C Symbol Expression — F SCL T SCL T BUF T SU;STA T HD;STA DSP56367 Technical Data, Rev. 2.1 141 147 144 144 153 151 LSB 148 149 LSB Valid 158 AA0274 Standard Fast-Mode Min Max Min Max — ...
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... C T AS;RQI × 0 CCP × 0 HO;RQI = Standard Mode Fast Mode. DSP56367 Technical Data, Rev. 2.1 2 Serial Host Interface (SHI Protocol Timing Standard Fast-Mode Min Max Min Max 4.7 — 1.3 4.0 — 1.3 × — 1000 20 + 0.1 C ...
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... × × × 10ns × × × CCP DSP56367 Technical Data, Rev. 2 × HRS ) – and the filters selected should be chosen Table 3-18. × 45ns + R C × 135ns + R C × ...
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... C Timing Symbol Expression t SSICC TXC:max[3*tc; — 2 × − 10.0 — 2 × − 10.0 — — 8 — 8 — DSP56367 Technical Data, Rev. 2.1 Enhanced Serial Audio Interface Timing ACK Stop 183 187 AA0275 1, 2 Min Max Condition 4 × 26.8 — × 20.1 — ...
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... Symbol Expression — — — — 8 — — — — — — — 8 — 8 — — — — — DSP56367 Technical Data, Rev. 2 (continued) Min Max Condition — — 36 — 21 — — 37 — 22 — 0.0 — ...
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... Freescale Semiconductor Symbol Expression 23 + 0.5 × — 9 — — — — — — — — — — — DSP56367 Technical Data, Rev. 2.1 Enhanced Serial Audio Interface Timing 1, 2 (continued) Min Max Condition — 26 21.0 — 21 — — 31 — 16 — ...
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... In normal mode, the output flag state is asserted for the entire frame period. 3-48 430 432 446 447 450 454 454 452 First Bit 459 453 461 458 461 460 462 Figure 3-32 ESAI Transmitter Timing DSP56367 Technical Data, Rev. 2.1 451 455 Last Bit 456 See Note AA0490 Freescale Semiconductor ...
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... Freescale Semiconductor 430 431 432 433 434 437 439 First Bit 441 443 442 444 Figure 3-33 ESAI Receiver Timing 463 464 Figure 3-34 ESAI HCKT Timing DSP56367 Technical Data, Rev. 2.1 Enhanced Serial Audio Interface Timing 438 440 Last Bit 443 445 AA0491 3-49 ...
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... ACI low duration 223 ACI rising edge to ADO valid 1 In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the DSP56367 internal clock frequency. For example, if the DSP56367 is running at 150 MHz internally, the ACI frequency should be less than 75 MHz. ACI ...
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... Valid only when PLL enabled with multiplication factor equal to one. Freescale Semiconductor 1 Table 3-21 Timer Timing Expression 2 × 2 × 2 480 481 Table 3-22 GPIO Timing DSP56367 Technical Data, Rev. 2.1 Timer Timing 150 MHz Unit Min Max 15.4 — ns 15.4 — ns AA0492 Expression Min Max Unit — 32.8 4.8 — ...
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... TCK low to output high impedance 508 TMS, TDI data setup time 3-52 492 493 Valid 494 495 496 Figure 3-38 GPIO Timing 1, 2 Table 3-23 JTAG Timing Characteristics × 3); maximum 22 MHz) C DSP56367 Technical Data, Rev. 2.1 490 491 All frequencies Unit Min Max 0.0 22.0 MHz 45.0 — ns 20.0 — ns ...
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... Table 3-23 JTAG Timing (continued) Characteristics = 501 502 504 Input Data Valid 506 Output Data Valid 507 506 Output Data Valid DSP56367 Technical Data, Rev. 2.1 JTAG Timing All frequencies Min Max 25.0 — 0.0 44.0 0.0 44.0 502 V M 503 AA0496 V IH 505 AA0497 ...
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... JTAG Timing TCK V (Input) IL TDI TMS (Input) TDO (Output) TDO (Output) TDO (Output) Figure 3-41 Test Access Port Timing Diagram 3-54 508 Input Data Valid 510 Output Data Valid 511 510 Output Data Valid DSP56367 Technical Data, Rev. 2 509 AA0498 Freescale Semiconductor ...
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... Pin-out and Package Information This section provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated for the package. The DSP56367 is available in a 144-pin LQFP package. assignments for the packages. 4.1.1 ...
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... HRW/HRD 22 HACK/HRRQ 23 HOREQ/HTRQ 24 VCCS 25 GNDS 26 ADO 27 ACI 28 TIO0 29 HCS/HA10 30 HA9/HA2 31 HA8/HA1 32 HAS/HA0 33 HAD7 34 HAD6 35 HAD5 36 4-2 Figure 4-1 144-pin package DSP56367 Technical Data, Rev. 2.1 108 D6 107 D5 106 D4 105 D3 104 GNDD 103 VCCD 102 D2 101 D1 100 D0 99 A17 98 A16 97 A15 96 GNDA 95 VCCQH 94 A14 93 A13 ...
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... MODC/IRQC# 58 MODD/IRQD# 66 MISO/SDA 104 MOSI/HA0 112 PCAP 120 PINIT/NMI# 130 RD# 39 RESET# 47 SCK/SCL 19 SCKR 54 SCKR_1 90 SCKT 127 SCKT_1 DSP56367 Technical Data, Rev. 2.1 Pin-out and Package Information Pin Signal Name No. 9 SDO0/SDO0_1 26 SDO1/SDO1_1 32 SDO2/SDI3/SDO2_1/SDI3_1 31 SDO3/SDI2/SDO3_1/SDI2_1 23 SDO4/SDI1 43 SDO4_1/SDI1_1 42 SDO5/SDI0 41 SDO5_1/SDI0_1 40 SS#/HA2 37 TA# ...
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... WR# 103 VCCD 68 RD# 104 GNDD 69 AA1 105 D3 70 AA0 106 D4 71 BG# 107 108 D6 DSP56367 Technical Data, Rev. 2.1 Pin Signal Name Signal Name No. 109 D7 110 D8 111 VCCD 112 GNDD 113 D9 114 D10 115 D11 116 D12 117 D13 118 D14 ...
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... LQFP Package Mechanical Drawing Figure 4-2 DSP56367 144-pin LQFP Package ( Freescale Semiconductor DSP56367 Technical Data, Rev. 2.1 Pin-out and Package Information 4-5 ...
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... Pin-out and Package Information Figure 4-3 DSP56367 144-pin LQFP Package ( 4-6 DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
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... Figure 4-4 DSP56367 144-pin LQFP Package ( Freescale Semiconductor DSP56367 Technical Data, Rev. 2.1 Pin-out and Package Information 4-7 ...
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... Pin-out and Package Information 4-8 DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
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... Freescale Semiconductor , in °C can be obtained from the following equation × θ θJA θJC θCA . For example, the user can change the air flow around θCA θJA DSP56367 Technical Data, Rev. 2.1 do not satisfactorily answer whether 5-1 ...
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... IRQB, IRQD, and TA pins. Maximum PCB trace lengths on the order inches) are recommended. 5 determined by a thermocouple, the thermal resistance T CAUTION ). The suggested value for a pull-up or pull-down resistor CC power source to GND. CC DSP56367 Technical Data, Rev. 2.1 – has been defined JT pin on the DSP and from CC and GND ...
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... Take special care to minimize noise levels on the V • If multiple DSP56367 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. • RESET must be asserted when the chip is powered up. A stable EXTAL signal must be supplied before deassertion of RESET. • ...
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... The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values. 5-4 Appendix A, "Power Consumption ⁄ MHz = I – I typF2 typF1 NOTE DSP56367 Technical Data, Rev. 2.1 ⁄ – Freescale Semiconductor ...
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... BCR: Area w.s (SRAM) ; Default: 1 w.s (SRAM) ; movep #$0d0000,x:M_PCTL ; ; Load the program ; move #INT_PROG,r0 move #PROG_START,r1 do #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ nop PLOAD_LOOP ; ; Load the X-data ; move #INT_XDAT,r0 move #XDAT_START,r1 Freescale Semiconductor ; XTAL disable ; PLL enable ; CLKOUT disable DSP56367 Technical Data, Rev. 2.1 A-1 ...
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... PROG_END nop nop XDAT_START ; org x:0 dc $262EB9 dc $86F2FE dc $E56A5F dc $616CAC A-2 ; ebd x:(r0)+,x1 y:(r4)+,y1 x:(r0)+,x0 y:(r4)+,y0 x:(r0)+,x1 y:(r4)+,y0 DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
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... Freescale Semiconductor DSP56367 Technical Data, Rev. 2.1 A-3 ...
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... A-4 DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
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... YDAT_END Freescale Semiconductor DSP56367 Technical Data, Rev. 2.1 A-5 ...
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... A-6 NOTES DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
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... EXTAL jitter 4 external address bus 4 external bus control external clock operation 4 external data bus 4 external interrupt timing (negative edge-triggered) 11 external level-sensitive fast interrupt timing 10 external memory access (DMA Source) timing 12 External Memory Expansion Port 4, 12 DSP56367 Technical Data, Rev. 2.1 Index-1 ...
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... P package TQFP description 1, 4 Phase Lock Loop 6 PLL 4, 6 Characteristics 6 performance issues 4 PLL design considerations 4 PLL performance issues 4 Port A 4 Port Port C 13, 16 Port D 18 Power 2 power consumption design considerations 3 DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
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... General Purpose I/O (GPIO) Timing 45 OnCE™ (On Chip Emulator) Timing 45 Serial Host Interface (SHI) SPI Protocol Tim- ing 37 Serial Host Interface (SHI) Timing 37 timing Freescale Semiconductor interrupt 7 mode select 7 Reset 7 Stop 7 TQFP pin list by number 4 pin-out drawing (top) 1 DSP56367 Technical Data, Rev. 2.1 Index-3 ...
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... Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com DSP56367 Document Number: Rev. 2.1 1/2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...