xc3s1400an Xilinx Corp., xc3s1400an Datasheet
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xc3s1400an Summary of contents
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... Pin Descriptions • Package Overview • Pinout Tables • Footprint Diagrams Spartan-3AN FPGA XC3S1400AN www.xilinx.com Bitstream Sizes Detailed Descriptions by Mode · Self-contained In-System Flash mode · Master Serial Mode using Platform Flash PROM · Master SPI Mode using Commodity Serial Flash · ...
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R DS557 June 2, 2008 ...
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... XC3S700AN 700K 13,248 1472 XC3S1400AN 1400K 25,344 2816 Notes convention, one Kb is equivalent to 1,024 bits and one Mb is equivalent to 1,024 Kb. 2. The XC3S400AN and the XC3S700AN have the same number of block RAMs and multipliers because the XC3S700AN adds DCMs as shown in Figure 1 ...
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... DCM IOBs Notes: 1. The XC3S700AN and XC3S1400AN have two additional DCMs on both the left and right sides as indicated by the dashed lines. The XC3S50AN has only two DCMs at the top and only one Block RAM/Multiplier column. 4 • Digital Clock Manager (DCM) Blocks provide ...
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... Part Number XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN 1. Aligned to next available page location. After configuration, the FPGA design has full access to the in-system Flash memory via an internal SPI interface; the control logic is implemented with FPGA logic. Additionally, the FPGA application itself can store nonvolatile data or provide live, in-system Flash updates ...
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... XC3S400AN – XC3S700AN – XC3S1400AN – Notes: 1. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number of input-only pins. The Diff input-only pin count includes dedicated inputs and differential pins on banks restricted to inputs. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins within I/O banks that are restricted to differential inputs ...
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R Package Marking Figure 3 provides a top marking example for Spartan-3AN FPGAs in the quad-flat packages. Figure 4 marking for Spartan-3AN FPGAs in BGA packages. The markings for the BGA packages are nearly identical to those for the quad-flat ...
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... Package Type Device Speed Grade XC3S50AN –4 Standard Performance TQG144 XC3S200AN –5 High Performance XC3S400AN XC3S700AN XC3S1400AN Notes: 1. The –5 speed grade is exclusively available in the Commercial temperature range. 2. See Table 3 for available package combinations. Revision History The following table shows the revision history for this document. ...
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R DS557-2 (v3.1) June 2, 2008 Spartan-3AN FPGA Design Documentation ® The functionality of the Spartan -3AN FPGA family is described in the following documents. The topics covered in each guide are listed below: • UG331: Spartan-3 Generation FPGA User ...
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Functional Description Related Product Families The Spartan-3AN FPGA family is generally compatible with the Spartan-3A FPGA family. • DS529: Spartan-3A FPGA Family Data Sheet http://www.xilinx.com/support/documentation/ data_sheets/ds529.pdf Revision History The following table shows the revision history for this document. Date Version ...
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R DS557-3 (v3.1) June 2, 2008 DC Electrical Characteristics In this section, specifications can be designated as Advance, Preliminary, or Production. These terms are defined as follows: Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the ...
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DC and Switching Characteristics Power Supply Specifications Table 5: Supply Voltage Thresholds for Power-On Reset Symbol V Threshold for the V CCINTT V Threshold for the V CCAUXT V Threshold for the V CCO2T Notes: 1. When configuring from the ...
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R General Recommended Operating Conditions Table 8: General Recommended Operating Conditions Symbol T Junction temperature J V Internal supply voltage CCINT (1) V Output driver supply voltage CCO V Auxiliary supply voltage CCAUX (2) V Input voltage IN T Input ...
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DC and Switching Characteristics General DC Characteristics for I/O Pins Table 9: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol Description I Leakage current at User I/O, L Input-only, Dual-Purpose, and Dedicated pins, FPGA powered I Leakage ...
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... XC3S1400AN 0.3 XC3S50AN 3.1 XC3S200AN 5.1 XC3S400AN 5.1 XC3S700AN 6.1 XC3S1400AN 10.1 Table 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, a design with no CCAUX provides quick, approximate, typical estimates, and does not require a netlist of the design, and b) www.xilinx.com DC and Switching Characteristics Commercial Industrial ...
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DC and Switching Characteristics Single-Ended I/O Standards Table 11: Recommended Operating Conditions for User I/Os Using Single-Ended Standards V for Drivers CCO IOSTANDARD Attribute Min (V) Nom (V) LVTTL 3.0 (4) LVCMOS33 3.0 (4,5) LVCMOS25 2.3 (4) LVCMOS18 1.65 (4) ...
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R Table 12: DC Characteristics of User I/Os Using Single-Ended Standards Test Conditions I I IOSTANDARD OL OH Attribute (mA) (mA) (3) LVTTL 2 2 – – – – – ...
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DC and Switching Characteristics Differential I/O Standards Differential Input Pairs Internal Logic V V GND level Table 13: Recommended Operating Conditions for User I/Os Using Differential Signal Standards V CCO IOSTANDARD Attribute Min (V) (3) LVDS_25 2.25 (3) LVDS_33 3.0 ...
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R Differential Output Pairs Internal Logic V OUTN V OUTP GND level Table 14: DC Characteristics of User I/Os Using Differential Signal Standards IOSTANDARD Attribute Min (mV) LVDS_25 247 LVDS_33 247 BLVDS_25 240 MINI_LVDS_25 300 MINI_LVDS_33 300 RSDS_25 100 RSDS_33 ...
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DC and Switching Characteristics External Termination Requirements for Differential I/O LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards 2.5V CCO CCO LVDS_33, LVDS_25, MINI_LVDS_33, MINI_LVDS_25, RSDS_33, RSDS_25, PPDS_33 PPDS_25 a) Input-only Differential Pairs or Pairs not ...
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R Device DNA Read Endurance Table 15: Device DNA Identifier Memory Characteristics Symbol Number of READ operations or JTAG ISC_DNA read operations. Unaffected by DNA_CYCLES HOLD or SHIFT operations In-System Flash Memory Data Retention, Program/Write Endurance Table 16: In-System Flash ...
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... Xilinx development software) and back-annotated to the simulation netlist. Table 17: Spartan-3AN Family v1.39 Speed Grade Designations Device XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN Table 18 provides the recent history of the Spartan-3AN speed files. Table 18: Spartan-3AN Speed File Version History Version 1.39 ISE 9.2.03i Updated to Production. No change to 1.38 1 ...
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... Fast slew XC3S200AN (3) rate, with DCM XC3S400AN XC3S700AN XC3S1400AN (2) LVCMOS25 , 12mA XC3S50AN output drive, Fast slew XC3S200AN rate, without DCM XC3S400AN XC3S700AN XC3S1400AN Table 28 and are based on the operating conditions set forth in www.xilinx.com DC and Switching Characteristics Speed Grade -5 -4 Max Max Units 3.18 3.42 ns 3.21 3. ...
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... XC3S200AN (4) with DCM XC3S400AN XC3S700AN XC3S1400AN (3) LVCMOS25 , XC3S50AN IFD_DELAY_VALUE = 5, XC3S200AN without DCM XC3S400AN XC3S700AN XC3S1400AN Table 28 and are based on the operating conditions set forth in Table 24. If this is true of the data Input, add the Table www.xilinx.com Speed Grade -5 -4 Min Min Units 2.45 2. ...
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... IOPICKD Input pin to the active transition at the ICLK input of the Input Flip-Flop (IFF). The Input Delay is programmed. DS557-3 (v3.1) June 2, 2008 Product Specification IFD_ DELAY_ Conditions Device VALUE (2) LVCMOS25 0 XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN (2) LVCMOS25 1 XC3S50AN XC3S200AN ...
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... IFD_ DELAY_ Conditions Device VALUE (2) LVCMOS25 1 XC3S700AN XC3S1400AN (2) LVCMOS25 0 XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN (2) LVCMOS25 1 XC3S50AN XC3S200AN www.xilinx.com R Speed Grade -5 -4 Min Min Units 1.82 1.95 ns 2.62 2. ...
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... XC3S700AN –1.67 2 –2.27 3 –2.59 4 –2.92 5 –2.89 6 –3.22 7 –3.52 8 –3.81 1 XC3S1400AN –1.60 2 –2.06 3 –2.46 4 –2.86 5 –2.88 6 –3.24 7 –3.55 8 –3.89 - All 1.33 and are based on the operating conditions set forth in -4 Min Units –1.12 ns –1.70 ns –2.08 ns –2.38 ns – ...
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... The time it takes for data to travel IOPLID from the Input pin through the IFF latch to the I output with the input delay programmed 28 IFD_ DELAY_ Conditions Device VALUE (2) LVCMOS25 0 XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN (2 LVCMOS25 1 XC3S50AN XC3S200AN ...
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... This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is true, add the appropriate Input adjustment from DS557-3 (v3.1) June 2, 2008 Product Specification (Continued) IFD_ DELAY_ Conditions Device VALUE (2 LVCMOS25 1 XC3S1400AN Table 28 and are based on the operating conditions set forth in Table 24. www.xilinx.com ...
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DC and Switching Characteristics Input Timing Adjustments Table 24: Input Timing Adjustments by IOSTANDARD Adjustment Below Convert Input Time from LVCMOS25 to the Following Speed Grade Signal Standard (IOSTANDARD) -5 Single-Ended Standards LVTTL 0.62 LVCMOS33 0.54 LVCMOS25 0 LVCMOS18 0.83 ...
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R Output Propagation Times Table 25: Timing for the IOB Output Path Symbol Description Clock-to-Output Times T When reading from the Output IOCKP Flip-Flop (OFF), the time from the active transition at the OCLK input to data appearing at the ...
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DC and Switching Characteristics Three-State Output Propagation Times Table 26: Timing for the IOB Three-State Path Symbol Description Synchronous Output Enable/Disable Times T Time from the active transition at the OTCLK IOCKHZ input of the Three-state Flip-Flop (TFF) to when ...
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R Output Timing Adjustments Table 27: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL Slow ...
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DC and Switching Characteristics Table 27: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) LVCMOS25 Slow ...
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R Table 27: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Differential Standards LVDS_25 LVDS_33 BLVDS_25 MINI_LVDS_25 MINI_LVDS_33 LVPECL_25 LVPECL_33 RSDS_25 RSDS_33 TMDS_33 PPDS_25 PPDS_33 ...
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DC and Switching Characteristics Timing Measurement Methodology When measuring timing parameters at the programmable I/Os, different signal standards call for different test conditions. Table 28 lists the conditions to use for each standard. The method for measuring Input timing is ...
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R Table 28: Test Methods for Timing Measurement at I/Os (Continued) Signal Standard (IOSTANDARD) V (V) REF Differential LVDS_25 - LVDS_33 - BLVDS_25 - MINI_LVDS_25 - MINI_LVDS_33 - LVPECL_25 - LVPECL_33 - RSDS_25 - RSDS_33 - TMDS_33 - PPDS_25 - ...
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... Ball grid array packages are recommended for applications with a large number of simultaneously switching outputs. Table 29: Equivalent V Device XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN CCO www.xilinx.com and Table 30 provide the essential SSO /GND pairs. The CCO Table 30 ...
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R Table 30: Recommended Number of Simultaneously Switching Outputs per V -GND Pair CCO TQG144 Top, Bottom Signal Standard (Banks (IOSTANDARD) 0,2) Single-Ended Standards LVTTL Slow ...
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DC and Switching Characteristics Table 30: Recommended Number of Simultaneously Switching Outputs per V -GND Pair (Continued) CCO TQG144 Top, Bottom Signal Standard (Banks (IOSTANDARD) 0,2) LVCMOS25 Slow – ...
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R Table 30: Recommended Number of Simultaneously Switching Outputs per V -GND Pair (Continued) CCO TQG144 Top, Bottom Signal Standard (Banks (IOSTANDARD) 0,2) Differential Standards (Number of I/O Pairs or Channels) LVDS_25 8 LVDS_33 8 BLVDS_25 1 MINI_LVDS_25 8 MINI_LVDS_33 ...
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DC and Switching Characteristics Configurable Logic Block (CLB) Timing Table 31: CLB (SLICEM) Timing Symbol Clock-to-Output Times T When reading from the FFX (FFY) Flip-Flop, the time CKO from the active transition at the CLK input to data appearing at ...
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R Table 32: CLB Distributed RAM Switching Characteristics Symbol Clock-to-Output Times T Time from the active edge at the CLK input to data appearing on SHCKO the distributed RAM output Setup Times T Setup time of data at the BX ...
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DC and Switching Characteristics Clock Buffer/Multiplexer Switching Characteristics Table 34: Clock Distribution Switching Characteristics Description Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same as ...
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Embedded Multiplier Timing Table 35 Embedded Multiplier Timing Symbol Combinatorial Delay T Combinational multiplier propagation delay from the A and B inputs MULT to the P outputs, assuming 18-bit inputs and a 36-bit ...
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DC and Switching Characteristics Block RAM Timing Table 36: Block RAM Timing Symbol Clock-to-Output Times T When reading from block RAM, the delay from the active RCKO transition at the CLK input to data appearing at the DOUT output Setup ...
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R Digital Clock Manager (DCM) Timing For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS). Aspects of DLL operation play a role in all DCM ...
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DC and Switching Characteristics Table 38: Switching Characteristics for the DLL Symbol Output Frequency Ranges CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs CLKOUT_FREQ_2X Frequency for the CLK2X and CLK2X180 outputs CLKOUT_FREQ_DV ...
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R Digital Frequency Synthesizer (DFS) Table 39: Recommended Operating Conditions for the DFS Symbol (2) Input Frequency Ranges F CLKIN_FREQ_FX Frequency for the CLKIN input CLKIN (3) Input Clock Jitter Tolerance CLKIN_CYC_JITT_FX_LF Cycle-to-cycle jitter at the CLKIN input, based on ...
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DC and Switching Characteristics Table 40: Switching Characteristics for the DFS (Continued) Symbol Lock Time (2) LOCK_FX The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when the ...
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R Phase Shifter (PS) Table 41: Recommended Operating Conditions for the PS in Variable Phase Mode Symbol Operating Frequency Ranges PSCLK_FREQ Frequency for the PSCLK input (F ) PSCLK Input Pulse Requirements PSCLK_PULSE PSCLK pulse width as a percentage of ...
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DC and Switching Characteristics Miscellaneous DCM Timing Table 43: Miscellaneous DCM Timing Symbol DCM_RST_PW_MIN Minimum duration of a RST pulse width (2) DCM_RST_PW_MAX Maximum duration of a RST pulse width (3) DCM_CONFIG_LAG_TIME Maximum duration from V configuration successfully completed (DONE ...
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... XC3S50AN 13 32 XC3S200AN XC3S400AN XC3S700AN 15 35 XC3S1400AN XC3S50AN 14 35 XC3S200AN XC3S400AN XC3S700AN XC3S1400AN 17 40 XC3S50AN 15 35 XC3S200AN 30 75 XC3S400AN XC3S700AN 45 100 XC3S1400AN XC3S50AN 0.8 2.5 XC3S200AN 1.6 5 XC3S400AN XC3S700AN XC3S1400AN Units ns MHz MHz MHz ns ns Units μ s μ ...
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DC and Switching Characteristics Suspend Mode Timing Entering Suspend Mode SUSPEND Input AWAKE Output Flip-Flops, Block RAM, Distributed RAM FPGA Outputs FPGA Inputs, Interconnect Table 47: Suspend Mode Timing Parameters Symbol Entering Suspend Mode T Rising edge of SUSPEND pin ...
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... This means power must be applied to all V Spartan-3 Generation Configuration User Guide. www.xilinx.com DC and Switching Characteristics 1.2V 3.3V 2.5V or 3.3V T ICCK DS557-3_01_052908 , V , and V CCINT CCAUX CCO All Speed Grades Device Min Max All - 18 All 0.5 - XC3S50AN - 0.5 XC3S200AN - 0.5 XC3S400AN - 1 XC3S700AN - 2 XC3S1400AN - 2 All 250 - All 0.5 4 Units ms μ μ CCINT CCO 55 ...
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DC and Switching Characteristics Configuration Clock (CCLK) Characteristics Table 49: Master Mode CCLK Output Period by ConfigRate Option Setting Symbol Description CCLK clock period by T ConfigRate setting CCLK1 T CCLK3 T CCLK6 T CCLK7 T CCLK8 T CCLK10 T ...
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R Table 50: Master Mode CCLK Output Frequency by ConfigRate Option Setting Symbol Description Equivalent CCLK clock frequency F by ConfigRate setting CCLK1 F CCLK3 F CCLK6 F CCLK7 F CCLK8 F CCLK10 F CCLK12 F CCLK13 F CCLK17 F ...
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DC and Switching Characteristics Master Serial and Slave Serial Mode Timing PROG_B (Input) INIT_B (Open-Drain) CCLK (Input/Output) DIN (Input) DOUT (Output) Figure 13: Waveforms for Master Serial and Slave Serial Configuration Table 53: Timing for the Master Serial and Slave ...
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R Slave Parallel Mode Timing PROG_B (Input) INIT_B (Open-Drain) CSI_B (Input) RDWR_B (Input) CCLK (Input (Inputs) Notes possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low ...
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DC and Switching Characteristics External Serial Peripheral Interface (SPI) Configuration Timing PROG_B (Input) PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process. (Input) VS[2:0] <1:1:1> (Input) M[2:0] <0:0:1> (Input) T MINIT INIT_B (Open-Drain) CCLK ...
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R Table 56: Configuration Timing Requirements for Attached SPI Serial Flash Symbol T SPI serial Flash PROM chip-select time CCS T SPI serial Flash PROM data input setup time DSU T SPI serial Flash PROM data input hold time DH ...
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DC and Switching Characteristics Byte Peripheral Interface (BPI) Configuration Timing PROG_B (Input) PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process. (Input) M[2:0] <0:1:0> (Input) T MINIT INIT_B (Open-Drain) LDC[2:0] HDC CSO_B CCLK A[25:0] ...
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R Table 58: Configuration Timing Requirements for Attached Parallel NOR Flash Symbol T Parallel NOR Flash PROM chip-select time ELQV T Parallel NOR Flash PROM output-enable time GLQV T Parallel NOR Flash PROM read ...
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... Configuration commands (CFG_IN, ISC_PROGRAM) All functions except ISC_DNA command During ISC_DNA command All operations on XC3S50AN, XC3S200AN, and XC3S400AN FPGAs and for BYPASS or HIGHZ instructions on all FPGAs All operations on XC3S700AN and XC3S1400AN FPGAs, except for BYPASS or HIGHZ instructions Table www.xilinx.com T T CCH ...
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... Initial release. 08/16/07 2.0 Updated for Production release of initial device (XC3S200AN). Timing specifications updated for v1.38 speed files. DC specifications updated with production values. Other changes throughout. 08/31/07 2.0.1 Updated for Production release of XC3S1400AN. Improved t 09/12/07 2.0.2 Updated for Production release of XC3S700AN. 09/24/07 2.1 Updated for Production release of XC3S400AN. Updated Production speed files are available as of Service Pack 3. Removed PCIX IOSTANDARD due to limited PCIX interface support ...
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DC and Switching Characteristics 66 www.xilinx.com R DS557-3 (v3.1) June 2, 2008 Product Specification ...
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R DS557-4 (v3.1) June 2, 2008 Introduction This section describes how the various pins on a ® Spartan -3AN FPGA connect within the supported component packages, and provides device-specific thermal characteristics. For general information on the pin functions and the ...
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... TQG144 108 XC3S200AN FTG256 195 XC3S400AN FGG400 311 XC3S700AN FGG484 372 XC3S1400AN FGG676 502 Notes: 1. Some VREFs are on INPUT pins. See pinout tables for details. 68 Description is available, as shown in maximum number of single-ended I/O pins available, assuming that all I/O-, INPUT-, DUAL-, VREF-, and CLK-type pins are used as general-purpose I/O. AWAKE is counted here as a Dual-Purpose I/O pin ...
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R Electronic versions of the package pinout tables and foot- prints are available for download from the Xilinx website: http://www.xilinx.com/support/documentation/data_sheets/ s3a_pin.zip Package Overview Table 63 shows the five low-cost, space-saving production package styles for the Spartan-3AN family. Table 63: Spartan-3AN ...
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... XC3S50AN FTG256 XC3S200AN FGG400 XC3S400AN FGG484 XC3S700AN FGG676 XC3S1400AN Notes: 1. Thermal characteristics are similar for leaded (non-Pb-free) packages. 70 The junction-to-case thermal resistance (θ difference between the temperature measured on the package body (case) and the junction temperature per watt of power consumption. The junction-to-board (θ ...
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R TQG144: 144-lead Thin Quad Flat Package The XC3S50AN is available in the 144-lead thin quad flat package, TQG144. Table 66 lists all the package pins. They are sorted by bank number and then by pin name. Pins that form ...
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Pinout Descriptions Table 66: Spartan-3AN TQG144 Pinout (Continued) Bank Pin Name 2 IO_L05N_2/D7 2 IO_L05P_2 2 IO_L06N_2/D6 2 IO_L06P_2 2 IO_L07N_2/D4 2 IO_L07P_2/D5 2 IO_L08N_2/GCLK15 2 IO_L08P_2/GCLK14 2 IO_L09N_2/GCLK1 2 IO_L09P_2/GCLK0 2 IO_L10N_2/GCLK3 2 IO_L10P_2/GCLK2 2 IO_L11N_2/DOUT 2 IO_L11P_2/AWAKE 2 ...
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R User I/Os by Bank Table 67 indicates how the 108 available user-I/O pins are distributed between the four I/O banks on the TQG144 package. The AWAKE pin is counted as a Dual-Purpose I/O. Table 67: User I/Os Per Bank ...
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Pinout Descriptions TQG144 Footprint Note pin 1 indicator in top-left corner and logo orientation. TMS 1 TDI 2 X IO_L02P_3 3 IO_L01P_3 4 IO_L02N_3 5 IO_L01N_3 6 IO_L03P_3 7 IO_L03N_3 8 GND 9 IO_L04P_3 10 IO_L04N_3/VREF_3 11 IO_L05P_3/LHCLK0 12 IO_L05N_3/LHCLK1 ...
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R FTG256: 256-ball Fine-pitch, Thin Ball Grid Array The 256-ball fine-pitch, thin ball grid array package, FTG256, supports the XC3S200AN FPGAs. Table 68 lists all the package pins. They are sorted by bank number and then by pin name of ...
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Pinout Descriptions Table 68: Spartan-3AN FTG256 Pinout (Continued) Bank Pin Name 1 IO_L14P_1/RHCLK4 1 IO_L15N_1/RHCLK7 1 IO_L15P_1/IRDY1/RHCLK6 1 IO_L16N_1/A11 1 IO_L16P_1/A10 1 IO_L17N_1/A13 1 IO_L17P_1/A12 1 IO_L18N_1/A15 1 IO_L18P_1/A14 1 IO_L19N_1/A17 1 IO_L19P_1/A16 1 IO_L20N_1/A19 1 IO_L20P_1/A18 1 IO_L22N_1/A21 1 ...
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R Table 68: Spartan-3AN FTG256 Pinout (Continued) Bank Pin Name 3 IO_L01N_3 3 IO_L01P_3 3 IO_L02N_3 3 IO_L02P_3 3 IO_L03N_3 3 IO_L03P_3 3 IO_L05N_3 3 IO_L05P_3 3 IO_L07N_3 3 IO_L07P_3 3 IO_L08N_3/VREF_3 3 IO_L08P_3 3 IO_L09N_3 3 IO_L09P_3 3 IO_L10N_3 ...
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Pinout Descriptions Table 68: Spartan-3AN FTG256 Pinout (Continued) Bank Pin Name VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT User I/Os by Bank Table 69 indicates how the ...
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R FTG256 Footprint (XC3S200AN I/O I/O A GND L19P_0 L18P_0 I/O I/O B TDI TMS L19N_0 L18N_0 I/O I/O I/O C GND L20P_0 L01N_3 L01P_3 VREF_0 I/O I/O I/O D VCCO_3 L03P_3 L02N_3 L02P_3 I/O I/O I/O ...
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Pinout Descriptions FGG400: 400-ball Fine-pitch Ball Grid Array The 400-ball fine-pitch ball grid array, FGG400, supports the XC3S400AN FPGA as shown in Table 70 Table 70 lists all the FGG400 package pins. They are sorted by bank number and then ...
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R Table 70: Spartan-3AN FGG400 Pinout (Continued) Bank Pin Name 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0/VREF_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 ...
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Pinout Descriptions Table 70: Spartan-3AN FGG400 Pinout (Continued) Bank Pin Name 1 IP_L04P_1 1 IP_L11N_1/VREF_1 1 IP_L11P_1 1 IP_L15N_1 1 IP_L15P_1/VREF_1 1 IP_L19N_1 1 IP_L19P_1 1 IP_L23N_1 1 IP_L23P_1/VREF_1 1 IP_L27N_1 1 IP_L27P_1 1 IP_L31N_1 1 IP_L31P_1/VREF_1 1 IP_L35N_1 1 ...
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R Table 70: Spartan-3AN FGG400 Pinout (Continued) Bank Pin Name 2 IO_L28P_2 2 IO_L29N_2 2 IO_L29P_2 2 IO_L30N_2 2 IO_L30P_2 2 IO_L31N_2 2 IO_L31P_2 2 IO_L32N_2/CCLK 2 IO_L32P_2/D0/DIN/MISO 2 IP_2 2 IP_2 2 IP_2 2 IP_2 2 IP_2 2 IP_2 ...
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Pinout Descriptions Table 70: Spartan-3AN FGG400 Pinout (Continued) Bank Pin Name 3 IO_L34P_3 3 IO_L36N_3 3 IO_L36P_3 3 IO_L37N_3 3 IO_L37P_3 3 IO_L38N_3 3 IO_L38P_3 3 IP_3 3 IP_L04N_3/VREF_3 3 IP_L04P_3 3 IP_L11N_3/VREF_3 3 IP_L11P_3 3 IP_L15N_3 3 IP_L15P_3 3 ...
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R Table 70: Spartan-3AN FGG400 Pinout (Continued) Bank Pin Name VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT ...
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Pinout Descriptions FGG400 Footprint Left Half of FGG400 Package (top view) I/O: Unrestricted, 155 general-purpose user I/O INPUT: Unrestricted, 46 general-purpose input pin DUAL: Configuration, 52 AWAKE pins, then possible user I/O VREF: User I/O or input 26 voltage reference ...
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R Bank I/O I/O I/O GND VCCAUX L13N_0 L07N_0 L08N_0 I/O I/O I/O I/O GND L14P_0 L13P_0 L11P_0 L08P_0 I/O I/O I/O I/O I/O L10N_0 L14N_0 L11N_0 L07P_0 L06N_0 VREF_0 I/O I/O I/O I/O ...
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Pinout Descriptions FGG484: 484-ball Fine-pitch Ball Grid Array The 484-ball fine-pitch ball grid array, FGG484, supports the XC3S700AN FPGA, as described in Table 72 lists all the FGG484 package pins. They are sorted by bank number and then by pin ...
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R Table 72: Spartan-3AN FGG484 Pinout (Continued) Bank Pin Name 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0/VREF_0 0 IP_0/VREF_0 0 IP_0/VREF_0 0 VCCO_0 0 VCCO_0 ...
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Pinout Descriptions Table 72: Spartan-3AN FGG484 Pinout (Continued) Bank Pin Name 1 IP_L12P_1 1 IP_L16N_1/VREF_1 1 IP_L16P_1 1 IP_L23N_1 1 IP_L23P_1 1 IP_L27N_1 1 IP_L27P_1/VREF_1 1 IP_L31N_1 1 IP_L31P_1 1 IP_L35N_1 1 IP_L35P_1/VREF_1 1 IP_L39N_1 1 IP_L39P_1 1 IP_L43N_1/VREF_1 1 ...
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R Table 72: Spartan-3AN FGG484 Pinout (Continued) Bank Pin Name 2 IO_L35P_2 2 IO_L36N_2/CCLK 2 IO_L36P_2/D0/DIN/MISO 2 IP_2 2 IP_2 2 IP_2 2 IP_2 2 IP_2 2 IP_2 2 IP_2 2 IP_2 2 IP_2 2 N.C. 2 N.C. 2 IP_2 ...
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Pinout Descriptions Table 72: Spartan-3AN FGG484 Pinout (Continued) Bank Pin Name 3 IO_L42N_3 3 IO_L42P_3 3 IO_L43N_3 3 IO_L43P_3 3 IO_L44N_3 3 IO_L44P_3 3 IO_L45N_3 3 IO_L45P_3 3 IP_3/VREF_3 3 IP_3/VREF_3 3 IP_L04N_3/VREF_3 3 IP_L04P_3 3 IP_L11N_3 3 IP_L11P_3 3 ...
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R Table 72: Spartan-3AN FGG484 Pinout (Continued) Bank Pin Name VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT ...
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Pinout Descriptions FGG484 Footprint Left Half of FGG484 Package (top view) I/O: Unrestricted, general-purpose user I/O 194 INPUT: Unrestricted, general-purpose input pin 61 DUAL: Configuration, 52 AWAKE pins, then possible user I/O VREF: User I/O or input voltage reference for ...
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R Bank I/O I/O I/O I/O I/O I/O L18P_0 L12N_0 L16N_0 L13N_0 L12P_0 L10N_0 GCLK6 VREF_0 I/O I/O I/O GND GND VCCO_0 L16P_0 L13P_0 L10P_0 I/O I/O I/O I/O I/O I/O L17P_0 L15N_0 ...
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... Pinout Descriptions FGG676: 676-ball Fine-pitch Ball Grid Array The 676-ball fine-pitch ball grid array, FGG676, supports the XC3S1400AN FPGA. Table 74 lists all the FGG676 package pins. They are sorted by bank number and then by pin name. Pairs of pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier ...
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R Table 74: Spartan-3AN FGG676 Pinout (Continued) Bank Pin Name 0 IO_L39P_0 0 IO_L40N_0 0 IO_L40P_0 0 IO_L41N_0 0 IO_L41P_0 0 IO_L42N_0 0 IO_L42P_0 0 IO_L43N_0 0 IO_L43P_0 0 IO_L44N_0 0 IO_L44P_0 0 IO_L45N_0 0 IO_L45P_0 0 IO_L46N_0 0 IO_L46P_0 ...
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Pinout Descriptions Table 74: Spartan-3AN FGG676 Pinout (Continued) Bank Pin Name 1 IO_L13N_1 1 IO_L13P_1 1 IO_L14N_1 1 IO_L14P_1 1 IO_L15N_1 1 IO_L15P_1 1 IO_L17N_1 1 IO_L17P_1 1 IO_L18N_1 1 IO_L18P_1 1 IO_L19N_1 1 IO_L19P_1 1 IO_L21N_1 1 IO_L21P_1 1 ...
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R Table 74: Spartan-3AN FGG676 Pinout (Continued) Bank Pin Name 1 IP_L24N_1/VREF_1 1 IP_L24P_1 1 IP_L28N_1 1 IP_L28P_1/VREF_1 1 IP_L32N_1 1 IP_L32P_1 1 IP_L36N_1 1 IP_L36P_1/VREF_1 1 IP_L40N_1 1 IP_L40P_1 1 IP_L44N_1 1 IP_L44P_1/VREF_1 1 IP_L48N_1 1 IP_L48P_1 1 IP_L52N_1/VREF_1 ...
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Pinout Descriptions Table 74: Spartan-3AN FGG676 Pinout (Continued) Bank Pin Name 2 IO_L32P_2/AWAKE 2 IO_L33N_2 2 IO_L33P_2 2 IO_L34N_2/D3 2 IO_L34P_2/INIT_B 2 IO_L35N_2 2 IO_L35P_2 2 IO_L36N_2/D1 2 IO_L36P_2/D2 2 IO_L37N_2 2 IO_L37P_2 2 IO_L38N_2 2 IO_L38P_2 2 IO_L39N_2 2 ...
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R Table 74: Spartan-3AN FGG676 Pinout (Continued) Bank Pin Name 3 IO_L06N_3 3 IO_L06P_3 3 IO_L07N_3 3 IO_L07P_3 3 IO_L09N_3 3 IO_L09P_3 3 IO_L10N_3 3 IO_L10P_3 3 IO_L11N_3 3 IO_L11P_3 3 IO_L13N_3 3 IO_L13P_3 3 IO_L14N_3 3 IO_L14P_3 3 IO_L15N_3 ...
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Pinout Descriptions Table 74: Spartan-3AN FGG676 Pinout (Continued) Bank Pin Name 3 IO_L59N_3 3 IO_L59P_3 3 IO_L60N_3 3 IO_L60P_3 3 IO_L61N_3 3 IO_L61P_3 3 IO_L63N_3 3 IO_L63P_3 3 IO_L64N_3 3 IO_L64P_3 3 IO_L65N_3 3 IO_L65P_3 3 IP_L04N_3/VREF_3 3 IP_L04P_3 3 ...
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R Table 74: Spartan-3AN FGG676 Pinout (Continued) Bank Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... Pinout Descriptions User I/Os by Bank Table 75 indicates how the 502 available user-I/O pins are distributed between the four I/O banks on the FGG676 package. The AWAKE pin is counted as a Dual-Purpose I/O. Table 75: User I/Os Per Bank for the XC3S1400AN in the FGG676 Package Package Edge I/O Bank Maximum I/O Top 0 ...
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R DS557-4 (v3.1) June 2, 2008 Product Specification www.xilinx.com Pinout Descriptions 105 ...
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... JTAG: Dedicated JTAG 4 port pins GND: Ground 77 VCCO: Output voltage 36 supply for bank VCCINT: Internal core supply voltage (+1.2V) 23 VCCAUX: Auxiliary supply voltage (+3.3V) 14 N.C.: Not connected Figure 22: XC3S1400AN FPGA in FGG676 Package Footprint (top view) 106 I/O I/O A GND INPUT GND L51P_0 L45P_0 I/O ...
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R Bank I/O I/O I/O I/O GND INPUT L26N_0 L23N_0 L18N_0 L15N_0 L14N_0 GCLK7 I/O I/O I/O I/O I/O L26P_0 VCCO_0 L14P_0 L23P_0 L19N_0 L18P_0 L15P_0 GCLK6 VREF_0 I/O I/O I/O I/O GND ...
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... Table 06/02/08 3.1 Add "Package Overview" unconnected N.C. pins for XC3S700AN FG484 in FGG676 in www.xilinx.com/spartan 108 Table 65. 65. Updated links. section. Removed VREF and INPUT designations and diamond symbols on Table 74 and Figure 22. www.xilinx.com Revision Table 72 and Figure 21 and for XC3S1400AN DS557-4 (v3.1) June 2, 2008 Product Specification R ...