ez80l92 ZiLOG Semiconductor, ez80l92 Datasheet - Page 15

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ez80l92

Manufacturer Part Number
ez80l92
Description
Ez80acclaim Flash Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet

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Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
PS013014-0107
Pin No
26
27
28
29
30
31
32
33
34
ADDR21
ADDR22
ADDR23
CS0
CS1
CS2
CS3
Symbol
V
V
DD
SS
Function
Address Bus
Address Bus
Address Bus
Chip Select 0
Chip Select 1
Chip Select 2
Chip Select 3
Power Supply
Ground
Signal Direction
Bidirectional
Bidirectional
Bidirectional
Output, Active Low
Output, Active Low
Output, Active Low
Output, Active Low
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
CS0 Low indicates that an access is
occurring in the defined CS0 memory or
I/O address space.
CS1 Low indicates that an access is
occurring in the defined CS1 memory or
I/O address space.
CS2 Low indicates that an access is
occurring in the defined CS2 memory or
I/O address space.
CS3 Low indicates that an access is
occurring in the defined CS3 memory or
I/O address space.
Power Supply.
Ground.
Description
Product Specification
Architectural Overview
9

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