ez80l92 ZiLOG Semiconductor, ez80l92 Datasheet - Page 158

• Manufacturer Part Number: ez80l92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS013014-0107
Table 81. I2C Slave Address Register (I2C_SAR = 00C8h)
I
The I2C_XSAR register is used in conjunction with the I2C_SAR register to provide 10-
bit addressing of the I
bits of the 10-bit slave address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}.
When the register receives an address starting with
the I
ACK after receiving the I2C_XSAR byte (the device does not generate an interrupt at this
point). After the next byte of the address (I2C_XSAR) is received, the I
interrupt and goes into SLAVE mode. Then I2C_SAR[2:1] are used as the upper 2 bits for
the 10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}. See
Table 82. I
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:1]
SLA
0
GCE
Bit
Reset
CPU Access
Note: R/W = Read/Write.
2
C Extended Slave Address Register
2
C recognizes that a 10-bit slave addressing mode is being selected. The I
2
C Extended Slave Address Register
00h–7Fh
Value
2
C when in SLAVE mode. The I2C_SAR value forms the lower 8
0
1
Table
R/W
R/W
7
0
7
0
82.
7-bit slave address or upper 2 bits,I2C_SAR[2:1],
Description
of address when operating in 10-bit mode.
I
I
2
2
C not enabled to recognize the General Call Address.
C enabled to recognize the General Call Address.
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
F7h
R/W
4
0
4
0
to
(I2C_XSAR = 00C9h)
F0h
R/W
R/W
3
0
3
0
(I2C_SAR[7:3] = 11110b),
Product Specification
R/W
R/W
2
0
2
0
I
2
C Serial I/O Interface
2
C generates an
R/W
R/W
1
0
1
0
2
C sends an
R/W
R/W
0
0
0
0
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