ade7753 Analog Devices, Inc., ade7753 Datasheet - Page 4

• Manufacturer Part Number: ade7753
• Description: Active And Apparent Energy Metering Ic With Di/dt Sensor Interface
• Manufacturer: Analog Devices, Inc.

ADE7753
ADE7753 TIMING CHARACTERISTICS
Parameter
Write timing
Read timing
1
2
3
4
NOTES
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5ns (10% to 90%)
and timed from a voltage level of 1.6V.
See timing diagram below and Serial Interface section of this data sheet.
Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8V or 2.4V.
Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit in Figure 1. The measured number is then extrapolated back to
remove the effects of charging or discharging the 50pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part
and is independent of the bus loading.
t
t
t
t
t
t
t
t
t
t
t
t
t
2
3
4
5
6
7
10
11
12
1
8
9
13
3
4
4
SCLK
DOUT
SCLK
DIN
DIN
CS
CS
A,B Versions
t
t
1
1
20
150
150
10
5
T BD
T BD
100
3.1
T BD
30
100
10
100
10
1
0
0
0
PRELIMINARY TECHNICAL DATA
t
2
0
Command Byte
0
t
Command Byte
3
Units
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
us (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
A4 A3 A2 A1 A0
t
A4 A3 A2 A1 A0
4
t
Test Conditions/Comments
CS falling edge to first SCLK falling edge
SCLK logic low pulse width
Valid Data Set up time before falling edge of SCLK
Data Hold time after SCLK falling edge
Minimum time between the end of data byte transfers.
Minimum time between byte transfers during a serial write.
CS Hold time after SCLK falling edge.
Minimum time between read command (i.e. a write to Communication
Reigster) and data read.
Minimum time between data byte transfers during a multibyte read.
Data access time after SCLK rising edge following a write to the
Communications Register
Bus relinquish time after falling edge of SCLK.
Bus relinquish time after rising edge of CS.
SCLK logic high pulse width
5
Serial Read Timing
Serial Write Timing
1,2
–4–
t
7
t
9
(AV
CLKIN = 3.579545MHz XTAL, TMIN to TMAX = -40°C to +85°C)
t
11
DD
DB7
Most Significant Byte
= DV
DB7
Most Significant Byte
DD
= 5V ± 5%, AGND = DGND = 0V, On-Chip Reference,
DB0
t
11
DB0
t
7
t
10
DB7
Least Significant Byte
Least Significant Byte
DB7
t
6
REV. PrF 10/02
t
12
DB0
t
DB0
13
t
8