ade7566acpzf8-rl Analog Devices, Inc., ade7566acpzf8-rl Datasheet - Page 135

• Manufacturer Part Number: ade7566acpzf8-rl
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Table 149. SPI Configuration SFR 2 (SPIMOD2, Address 0xE9)
Bit
7
6
5
4
3
2
1
0
Mnemonic
SPICONT
SPIEN
SPIODO
SPIMS_b
SPICPOL
SPICPHA
SPILSBF
TIMODE
Default
0
0
0
0
0
0
0
1
Description
Master mode, SPI continuous transfer mode enable bit.
SPICONT
0
1
SPI interface enable bit.
SPIEN
0
1
SPI open-drain output configuration bit.
SPIODO
0
1
SPI master mode enable bit.
SPIMS_b
0
1
SPI clock polarity configuration bit (see Figure 112).
SPICPOL
0
1
SPI clock phase configuration bit (see Figure 112).
SPICPHA
0
1
Master mode, LSB first configuration bit.
SPILSBF
0
1
Transfer and interrupt mode of the SPI interface.
TIMODE
1
Result
The SPI interface stops after one byte is transferred and SS is deasserted. A new data transfer
can be initiated after a stalled period.
The SPI interface continues to transfer data until no valid data is available in the SPI2CTx SFR.
SS remains asserted until the SPI2CTx SFR and the transmit shift registers are empty.
Result
The SPI interface is disabled.
The SPI interface is enabled.
Result
Internal pull-up resistors are connected to the SPI outputs.
The SPI outputs are open drain and need external pull-up resistors. The pull-up voltage should
not exceed the specified operating voltage.
Result
The SPI interface is defined as a slave.
The SPI interface is defined as a master.
Result
The default state of SCLK is low, and the first SCLK edge is rising. Depending on the SPICPHA bit,
the SPI data output changes state on the falling or rising edge of SCLK while the SPI data input is
sampled on the rising or falling edge of SCLK.
The default state of SCLK is high, and the first SCLK edge is falling. Depending on the SPICPHA
bit, the SPI data output changes state on the rising or falling edge of SCLK while the SPI data
input is sampled on the falling or rising edge of SCLK.
Result
The SPI data output changes state when SS goes low at the second edge of SCLK and then every
two subsequent edges, whereas the SPI data input is sampled at the first SCLK edge and then
every two subsequent edges.
The SPI data output changes state at the first edge of SCLK and then every two subsequent
edges, whereas the SPI data input is sampled at the second SCLK edge and then every two
subsequent edges.
Result
The MSB of the SPI outputs is transmitted first.
The LSB of the SPI outputs is transmitted first.
Result
This bit must be set to 1 for proper operation.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 135 of 152