mc68hc912bl16 Freescale Semiconductor, Inc, mc68hc912bl16 Datasheet
mc68hc912bl16
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mc68hc912bl16 Summary of contents
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... Technical Summary 16-Bit Microcontroller 1 Introduction The MC68HC912BL16 microcontroller unit (MCU 16-bit device composed of standard on-chip pe- ripherals including a 16-bit central processing unit (CPU12), 16-Kbyte flash EEPROM, 512-byte RAM, 512-byte EEPROM, an asynchronous serial communications interface (SCI), a serial peripheral inter- face (SPI), an 7-channel timer and 16-bit pulse accumulator, an 10-bit analog-to-digital converter (ADC), and a four-channel pulse-width modulator (PWM) ...
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... On-Chip Hardware Breakpoints 1.2 Ordering Information The MC68HC912BL16 is packaged in 64-pin quad flat pack (QFP) packaging and is shipped in two- piece sample packs, 50-piece trays, or 250-piece bricks. Operating temperature range and voltage re- quirements are specified when ordering the MC68HC912BL16 device. Refer to Table 1 for part num- bers ...
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... Freescale Semiconductor, Inc. Section 1 Introduction 1.1 Features ......................................................................................................................................1 1.2 Ordering Information ...................................................................................................................2 1.3 MC68HC912BL16 Block Diagram ...............................................................................................5 2 Central Processing Unit 2.1 Programming Model ....................................................................................................................6 2.2 Data Types ..................................................................................................................................7 2.3 Addressing Modes .......................................................................................................................7 2.4 Indexed Addressing Modes .........................................................................................................8 2.5 Opcodes and Operands ..............................................................................................................8 3 Pinout and Signal Descriptions 3.1 MC68HC912BL16 Pin Assignments ...........................................................................................9 3.2 Power Supply Pins ....................................................................................................................10 3.3 Signal Descriptions ....................................................................................................................11 3.4 Port Signals ...............................................................................................................................15 3 ...
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... Port S ......................................................................................................................................100 14 Analog-To-Digital Converter 14.1 Functional Description .............................................................................................................104 14.2 ATD Registers .........................................................................................................................104 14.3 ATD Mode Operation ..............................................................................................................111 15 Development Support 15.1 Instruction Queue ....................................................................................................................113 15.2 Background Debug Mode ........................................................................................................113 15.3 Breakpoints .............................................................................................................................122 15.4 Instruction Tagging ..................................................................................................................126 For More Information On This Product to: www.freescale.com Page 104 113 MC68HC912BL16 MC68HC912BL16TS/D ...
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... PE5 IPIPE0 / MODA PE6 IPIPE1 / MODB PE7 DBE MULTIPLEXED ADDRESS/DATA BUS DDRA PORT A WIDE BUS NARROW BUS Figure 1 MC68HC912BL16 Block Diagram For More Information On This Product, MC68HC912BL16TS/D ATD CONVERTER COP WATCHDOG CLOCK MONITOR BREAK POINTS TIMER AND OC7 PULSE ACCUMULATOR LITE ...
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... 8-BIT ACCUMULA TORS A & 16-BIT DOUBLE A CCUMULA TOR INDEX REGISTER INDEX REGISTER STACK POINTER PC 0 PROGRAM COUNTER CONDITION CODE REGISTER Figure 2 Programming Model Go to: www.freescale.com HC12 PROG MODEL MC68HC912BL16 MC68HC912BL16TS/D ...
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... Indexed-Indirect INST [oprx16,xysp] (16-bit offset) Indexed-Indirect (D accumulator INST [D,xysp] offset) For More Information On This Product, MC68HC912BL16TS/D Abbreviation INH Operands (if any) are in CPU registers Operand is included in instruction stream IMM 8- or 16-bit size implied by context Operand is the lower 8-bits of an address in the DIR range $0000 – ...
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... For More Information On This Product, 8 Comments rr SP 9-bit with sign in LSB of postbyte( 16-bit +8 = 0111 … 0000 -1 = 1111 … 1000 (16-bit see accumulator D offset indexed-indirect Go to: www.freescale.com -256 < n < 255 0 < n < 65,535 0 < n < 65,535 MC68HC912BL16 MC68HC912BL16TS/D ...
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... Freescale Semiconductor, Inc. 3 Pinout and Signal Descriptions 3.1 MC68HC912BL16 Pin Assignments The MC68HC912BL16 is available in a 64-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the 3.3 Signal Descriptions. Figure 3 shows pin assignments. Shaded pins are power and ground. IOC0 / PT0 ...
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... Freescale Semiconductor, Inc. 3.2 Power Supply Pins MC68HC912BL16 power and ground pins are described below and summarized in Table 4. 3.2.1 Internal Power (V ) and Ground (V DD Power is supplied to the MCU through V duration current demands on the power supply, use bypass capacitors with high-frequency character- istics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded ...
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... In special peripheral mode the E clock is an input to the MCU. All clocks, including the E-clock, are halted when the MCU is in STOP mode possible to configure the MCU to interface to slow external memory. ECLK can be stretched for such accesses. For More Information On This Product, MC68HC912BL16TS ...
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... External Address and Data Buses (ADDR[15:0] and DATA[15:0]) External bus pins share function with general-purpose I/O ports A and B. In single-chip operating modes, the pins can be used for I/O; in expanded modes, the pins are used for the external buses. For More Information On This Product to: www.freescale.com MC68HC912BL16 MC68HC912BL16TS/D ...
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... In expanded modes this pin is used to enable the drive control of external buses during ex- ternal reads only. Use of the DBE is controlled by the NDBE bit in the PEAR register. DBE is enabled out of reset in expanded modes. This pin has an active pull-up during and after reset in single-chip modes. For More Information On This Product, MC68HC912BL16TS/D Go to: www.freescale.com 13 ...
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... Freescale Semiconductor, Inc. Table 5 MC68HC912BL16 Signal Description Summary Pin Name Pin Number PW[3:0] 61–64 Pulse Width Modulator channel outputs. ADDR[7:0] 16–9 External bus pins share function with general-purpose I/O ports A and B. In sin- DATA[7:0] gle chip modes, the pins can be used for I/O. In expanded modes, the pins are ADDR[15:8] used for the external buses ...
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... Freescale Semiconductor, Inc. 3.4 Port Signals The MC68HC912BL16 incorporates eight ports which are used to control and access the various device subsystems. When not used for these purposes, port pins may be used for general-purpose I/O. In ad- dition to the pins described below, each port consists of a data register which can be read and written at any time, and, with the exception of port AD and PE[1:0], a data direction register which controls the direction of each pin ...
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... Port S is the 6-bit interface to the standard serial interface consisting of the serial communications in- terface (SCI) and serial peripheral interface (SPI) subsystems. Port S pins are available for general-pur- pose parallel I/O when standard serial functions are not enabled. For More Information On This Product to: www.freescale.com MC68HC912BL16 MC68HC912BL16TS/D ...
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... S pin which is programmed as a general-purpose input . If the pin is pro- grammed as a general-purpose output, the pull-up is disconnected from the pin regardless of the state of the individual PUPSx bits. See 13 Serial Interface. For More Information On This Product, MC68HC912BL16TS/D Go to: www.freescale.com 17 ...
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... Freescale Semiconductor, Inc. Table 6 MC68HC912BL16 Port Description Summary Pin Data Direction Port Name Numbers DD Register (Address) Port A In/Out 37–30 PA[7:0] DDRA ($0002) In/Out Port B 16–9 DDRB ($0003) PB[7:0] Port AD 49–42 PAD[7:0] PE[1:0] In Port E 20–17, 29–26 PE[7:2] In/Out PE[7:0] DDRE ($0009) Port P In/Out 61–64 ...
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... Pull-up PURDS ($00DB) PS[7:4] Pull-up PURDS ($00DB) Port T Pull-up TMSK2 ($008D) Port AD None BKGD Pull-up — For More Information On This Product, MC68HC912BL16TS/D Enable Bit Bit Name Reset State (Address) PUPA Disabled RDRIV ($000D) PUPB Disabled RDRIV ($000D) PUPE Enabled RDRIV ($000D) — ...
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... The register block occupies the first 512 bytes of the 2-Kbyte block. De- fault addressing (after reset) is indicated in the table below. For additional information refer to 5 Oper- ating Modes and Resource Mapping. Table 8 MC68HC912BL16 Register Map (Sheet Address Bit 7 ...
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... Freescale Semiconductor, Inc. Table 8 MC68HC912BL16 Register Map (Sheet Address Bit $0022 Bit $0023 Bit $0024 Bit $0025 Bit $0026– $003F $0040 CON23 CON01 PCKA2 $0041 PCLK3 PCLK2 PCLK1 $0042 $0043 $0044 ...
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... Freescale Semiconductor, Inc. Table 8 MC68HC912BL16 Register Map (Sheet Address Bit $006A– $006E $006F PAD7 PAD6 PAD5 $0070 Bit $0071 Bit $0072 Bit $0073 Bit $0074 Bit $0075 Bit $0076 Bit 15 14 ...
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... Freescale Semiconductor, Inc. Table 8 MC68HC912BL16 Register Map (Sheet Address Bit $0097 Bit $0098 Bit $0099 Bit $009A Bit $009B Bit $009C Bit $009D Bit $009E Bit $009F Bit $00A0 0 PAEN ...
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... Freescale Semiconductor, Inc. Table 8 MC68HC912BL16 Register Map (Sheet Address Bit $00E0 $00E1 TSTSMD BCSS 0 $00E2– $00EF $00F0 NOSEC 1 1 $00F1 $00F2 EEODD EEVEN MARG $00F3 BULKP 0 0 $00F4 $00F5 $00F6 FSTE GADR HVT ...
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... Freescale Semiconductor, Inc. 5 Operating Modes and Resource Mapping Eight possible operating modes determine the operating configuration of the MC68HC912BL16. Each mode has an associated default memory map and external bus configuration. After reset, most system resources can be mapped to other addresses by writing to the appropriate control registers. ...
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... EEPROM and Flash EEPROM without interrupting the application code executing in the CPU. This non- intrusive mode uses dead bus cycles to access the memory and in most cases will remain cycle deter- ministic. Refer to 16 Development Support for more details on BDM. For More Information On This Product to: www.freescale.com MC68HC912BL16 MC68HC912BL16TS/D ...
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... This bit controls access to the external bus interface when in wait mode. The module will delay before shutting down in wait mode to allow for final bus activity to complete External bus and registers continue functioning during wait mode External bus is shut down during wait mode. For More Information On This Product, MC68HC912BL16TS ...
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... This bit controls access to the memory mapping interface when in Wait mode. For More Information On This Product, 28 Table 10 Mapping Precedence Resource 1 BDM ROM (if active) 2 Register Space 3 RAM 4 EEPROM 5 Flash EEPROM 6 External Memory REG12 REG11 to: www.freescale.com $0011 1 Bit 0 0 MMSWAI 0 0 MC68HC912BL16 MC68HC912BL16TS/D ...
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... These bits specify the upper five bits of the 16-bit RAM address. Write once in normal modes or anytime in special modes. Read anytime. 5.3.3 EEPROM Mapping The MC68HC912BL16 has 512 bytes of EEPROM which is activated by the EEON bit in the INITEE register. Mapping of internal EEPROM is controlled by four bits in the INITEE register. After reset EEPROM ad- dress space begins at location $0E00 but can be mapped to any 4-Kbyte boundary within the standard 64-Kbyte address space ...
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... Flash EEPROM is located from $C000 to $FFFF For More Information On This Product RFSTR0 EXSTR1 EXSTR0 MAPROM ROMON to: www.freescale.com $0013 1 Bit Ex. Modes 1 1 Sing. Chip MC68HC912BL16 MC68HC912BL16TS/D ...
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... VECTORS VECTORS $FFFF EXPANDED SINGLE CHIP NORMAL Figure 6 MC68HC912BL16 Memory Map For More Information On This Product, MC68HC912BL16TS/D $0000 REGISTERS 512 BYTES RAM MAP TO ANY 2K SPACE $01FF $0200 REGISTER FOLLOWING SPACE 512 BYTES RAM $03FF ...
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... Freescale Semiconductor, Inc. 6 Bus Control and Input/Output Internally the MC68HC912BL16 has full 16-bit data paths, but depending upon the operating mode and control registers, the external bus may be eight or sixteen bits. There are cases where 8-bit and 16-bit accesses can appear on adjacent cycles using the LSTRB signal to indicate 8- or 16-bit data. ...
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... This register determines the primary direction for each port B pin when functioning as a general-purpose I/O port. DDRB is not in the on-chip map in expanded and peripheral modes. Read and write anytime Associated pin is a high-impedance input 1 = Associated pin is an output For More Information On This Product, MC68HC912BL16TS ...
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... Go to: www.freescale.com $0008 1 Bit 0 PE1 PE0 – – IRQ XIRQ $0009 1 Bit – – $000A 1 Bit Normal – – Expanded Special – – Expanded – – Peripheral Normal – – Single Chip Special – – Single Chip MC68HC912BL16 MC68HC912BL16TS/D ...
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... PE2 is configured as the R/W pin. In single-chip modes, RDWE has no effect and PE2 is a gen- eral-purpose I/O pin. R/W is used for external writes. After reset in normal expanded mode disabled. If needed it should be enabled before any external writes. For More Information On This Product, MC68HC912BL16TS/D Go to: www.freescale.com 35 ...
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... All port A output pins have full drive enabled All port A output pins have reduced drive capability. For More Information On This Product PUPE RDPE to: www.freescale.com $000C 1 Bit 0 PUPB PUPA 0 0 $000D 1 Bit 0 RDPB RDPA 0 0 MC68HC912BL16 MC68HC912BL16TS/D ...
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... Freescale Semiconductor, Inc. 7 Flash EEPROM The 16-Kbyte Flash EEPROM module for the MC68HC912BL16 serves as electrically erasable and programmable, non-volatile ROM emulation memory. The module can be used for program code that must either execute at high speed or is frequently executed, such as operating system kernels and stan- dard subroutines can be used for static data which is read frequently ...
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... For More Information On This Product FENLV FDISVFP VTCK pin low FP is low FP pin to control the control gate voltage; the FP (breakdown voltage) the control gate will equal the V 0. ZBRK FP ZBRK Go to: www.freescale.com $00F6 1 Bit 0 STRE MWPR 0 0 voltage. FP MC68HC912BL16 MC68HC912BL16TS/D ...
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... See Table 14 for the effects of LAT on array reads. A high volt- age detect circuit on the V pin will prevent assertion of the LAT bit when the programming voltage normal levels Programming latches disabled 1 = Programming latches enabled For More Information On This Product, MC68HC912BL16TS FEESWAI SVFP ...
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... For More Information On This Product, 40 ERAS Result of Read – Normal read of location addressed 0 Read of location being programmed 1 Normal read of location addressed – Read cycle is ignored Go to: www.freescale.com MC68HC912BL16 MC68HC912BL16TS/D ...
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... V be accomplished by plugging the board into a special programming fixture which provides program/erase voltage to the V For More Information On This Product, MC68HC912BL16TS/D ), the length of the program pulse ( the erase margin pulse or pulses, and EPULSE ...
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... If there are more locations to program, repeat steps 2 through 10. 12. Turn off V (reduce voltage The flowchart in Figure 7 demonstrates the recommended programming sequence. For More Information On This Product, 42 pin PPULSE ). VPROG pin to: www.freescale.com pin voltage MC68HC912BL16 MC68HC912BL16TS/D ...
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... Freescale Semiconductor, Inc. CLEAR PROGRAM PULSE COUNTER (n GET NEXT ADDRESS/DATA Figure 7 Program Sequence Flow For More Information On This Product, MC68HC912BL16TS/D START PROG TURN CLEAR MARGIN FLAG ) PP CLEAR ERAS SET LAT WRITE DATA TO ADDRESS SET ENPE DELAY FOR DURATION OF PROGRAM PULSE ...
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... This provides 100% erase margin. 9. Read the entire array to ensure that the Flash EEPROM is erased. 10. Clear LAT. 11. Turn off V (reduce voltage The flowchart in Figure 8 demonstrates the recommended erase sequence. For More Information On This Product, 44 pin EPULSE ). VERASE pin to: www.freescale.com ) EP MC68HC912BL16 MC68HC912BL16TS/D ...
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... Freescale Semiconductor, Inc. CLEAR ERASE PULSE COUNTER (n DELAY FOR DURATION DELAY BEFORE VERIFY NO For More Information On This Product, MC68HC912BL16TS/D START ERASE TURN CLEAR MARGIN FLAG ) EP SET ERAS SET LAT WRITE TO ARRAY SET ENPE OF ERASE PULSE (t ) EPULSE CLEAR ENPE (t ) VERASE INCREMENT ...
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... VDD is applied. Figure 9 shows the VFPE and VDD operating envelope. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for maximum and operating voltage specifications. For More Information On This Product supplied via an external pin CAUTION Go to: www.freescale.com FP MC68HC912BL16 MC68HC912BL16TS/D ...
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... C1. Allow for RC charge and discharge time constants when applying and removing power. When using this circuit, keep leakage from external devices connected to the VFPE pin low, to minimize diode voltage drop. For More Information On This Product, MC68HC912BL16TS MAXIMUM t er ...
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... Freescale Semiconductor, Inc Figure 10 V For More Information On This Product, 48 PROGRAMMING VOLTAGE POWER SUPPLY 4. 0.1 F Conditioning Circui FPE Go to: www.freescale.com V FPE PIN MC68HC912BL16 MC68HC912BL16TS/D ...
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... Freescale Semiconductor, Inc. 8 EEPROM The MC68HC912BL16 EEPROM serves as a 512-byte nonvolatile memory which can be used for fre- quently accessed static data or as fast access program code. The MC68HC912BL16 EEPROM is arranged in a 16-bit configuration. The EEPROM array may be read as either bytes, aligned words or misaligned words. Access times is one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations ...
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... Read and write anytime. For More Information On This Product, 50 SINGLE CHIP VECTORS RESERVED (64 BYTES) VECTORS (64 BYTES EESWAI PROTLCK PROG Go to: www.freescale.com $FF80 $FFBF $FFC0 $FFFF HC912BL16 EEPROM BLOCK PROT $00F0 1 Bit 0 EERC 0 0 MC68HC912BL16 MC68HC912BL16TS/D ...
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... MARG — Program and Erase Voltage Margin Test Enable 0 = Normal operation Program and erase margin test. This bit is used to evaluate the program/erase voltage margin. EECPD — Charge Pump Disable 0 = Charge pump is turned on during program/erase Disable charge pump. For More Information On This Product, MC68HC912BL16TS BPROT3 ...
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... For More Information On This Product, 52 pin BYTE ROW ERASE Table 16 Erase Selection Block Size 0 Bulk erase entire EEPROM array 1 Row erase 32 bytes 0 Byte or aligned word erase 1 Byte or aligned word erase NOTE Go to: www.freescale.com $00F3 1 Bit 0 EELAT EEPGM 0 0 MC68HC912BL16 MC68HC912BL16TS/D ...
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... Write a byte or an aligned word to an EEPROM address 3. Write EEPGM = 1 4. Wait for programming ( t 5. Write EEPGM = 0 6. Write EELAT = possible to program/erase more bytes or words without intermediate EEPROM reads, by jumping from step 5 to step 2. For More Information On This Product, MC68HC912BL16TS erase ( ) delay time t PROG ERASE Go to: www.freescale.com 53 ...
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... COPCTL (CME, FCME) None COP rate selected None None None None X bit None I bit INTCR (IRQEN) I bit RTICTL (RTIE) I bit TMSK1 (C0I) I bit TMSK1 (C1I) I bit TMSK1 (C2I) Go to: www.freescale.com HPRIO Value to Elevate – – – – – – $F2 $F0 $EE $EC $EA MC68HC912BL16 MC68HC912BL16TS/D ...
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... HPRIO — Highest Priority I Interrupt Bit PSEL5 RESET Write only if I mask in CCR = 1 (interrupts inhibited). Read anytime. For More Information On This Product, MC68HC912BL16TS/D Table 17 Interrupt Vector Map CCR Local Enable Mask Register (Bit) I bit TMSK1 (C3I) I bit TMSK1 (C4I) I bit ...
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... The RTIF flag is cleared and automatic hardware interrupts are masked. The rate control bits are cleared, and must be initialized before the RTI system is used. The DLY control bit is set to specify an oscillator start-up delay upon recovery from STOP mode. For More Information On This Product to: www.freescale.com MC68HC912BL16 MC68HC912BL16TS/D ...
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... If another interrupt is pending at the end of an interrupt service routine, the register unstacking and restacking is bypassed and the vector of the pending interrupt is fetched. For More Information On This Product, MC68HC912BL16TS/D CPU Registers SP – 2 RTN ...
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... Freescale Semiconductor, Inc. For More Information On This Product to: www.freescale.com MC68HC912BL16 MC68HC912BL16TS/D ...
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... Clock generation circuitry generates the internal and external E-clock signals as well as internal clock signals used by the CPU and on-chip peripherals. A clock monitor circuit, a computer operating properly (COP) watchdog circuit, and a periodic interrupt circuit are also incorporated into the MC68HC912BL16. 10.1 Clock Sources A compatible external clock signal can be applied to the EXTAL pin or the MCU can generate a clock signal using an on-chip oscillator circuit and an external crystal or ceramic resonator ...
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... Time-Out Period E = 4.0 MHz OFF OFF 13 2.048 4.096 8.196 16.384 32.768 65.536 131. to: www.freescale.com $0014 1 Bit 0 RTR1 RTR0 Time-Out Period E = 8.0 MHz OFF 1.024 ms 2.048 ms 4.096 ms 8.196 ms 16.384 ms 32.768 ms 65.536 ms MC68HC912BL16 MC68HC912BL16TS/D ...
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... These bits specify an additional division factor to arrive at the COP time-out rate (the clock used for this module is the E clock). Write once in normal modes, anytime in special modes. Read anytime. For More Information On This Product, MC68HC912BL16TS ...
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... OFF 1.024 ms 4.096 ms 16.384 ms 65.536 ms 262.144 ms 524.288 ms 1.048576 s $0017 1 Bit 0 1 Bit $00E0 1 Bit 0 SLDV1 SLDV0 0 0 Bus Rate w/ 4MHz XTAL 4 MHz 2 MHz 2 MHz 1 MHz 1 MHz 500 KHz 667 KHz 333 KHz 500 KHz 250 KHz MC68HC912BL16 MC68HC912BL16TS/D ...
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... Clock Divider Chains Figure 13, Figure 14, Figure 15, and Figure 16 summarize the clock divider chains for the various pe- ripherals on the MC68HC912BL16. The “intwai” signal in Figure 13, or wait mode, is the only mechanism for choosing slow clocks versus normal frequency clocks in normal operating modes. ...
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... Go to: www.freescale.com TCLKs TO CPU TO BDM, ECLK BUSES, SPI, ATD, SCI, TIM, RTI, COP, PWM, PCLK FEE, EE, RAM HC912BL16 CLOCK DIV CHAIN 0:0:0 REGISTER: COPCTL BITS: CR2, CR1, CR0 0:0:1 0:1:0 4 0:1 1:0:0 4 1:0:1 2 1:1:0 2 1:1:1 TO COP TO RTI HC912BL16 CLOCK CHAIN SCI RTI COP MC68HC912BL16 MC68HC912BL16TS/D ...
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... Figure 16 Clock Chain for SPI, ATD and BDM For More Information On This Product, MC68HC912BL16TS/D PULSE ACC LOW BYTE PULSE ACC PACLK HIGH BYTE PAMOD Figure 15 Clock Chain for TIM TO ATD 2 SPI BIT RATE BDM BIT CLOCK: ECLK Receive: Detect falling edge, ...
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... Freescale Semiconductor, Inc. For More Information On This Product to: www.freescale.com MC68HC912BL16 MC68HC912BL16TS/D ...
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... When PWM are not in use, the port pins may be used for discrete input/output. CLOCK SOURCE (ECLK) GATE PWCNTx (CLOCK EDGE SYNC) RESET PWENx PPOL = 0 PPOL = 1 Figure 17 Block Diagram of PWM Left-Aligned Output Channel For More Information On This Product, MC68HC912BL16TS/D CENTR = 0 UP/DOWN 8-BIT COMPARE = S PWDTYx 8-BIT COMPARE = PWPERx PWDTY PWPER Go to: www ...
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... Figure 18 Block Diagram of PWM Center-Aligned Output Channel For More Information On This Product, 68 CENTR = 1 RESET (DUTY CYCLE) 8-BIT COMPARE = PWDTYx T Q (PERIOD) Q 8-BIT COMPARE = PWPERx (PWPER PWDTY) 2 PWPER 2 Go to: www.freescale.com FROM PORT P DATA REGISTER MUX MUX TO PIN DRIVER PPOLx PWDTY MC68HC912BL16 MC68HC912BL16TS/D ...
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... Channel 2 output pin is used as the output for this 16-bit PWM (bit 2 of port P). Channel 3 clock- select control bits determines the clock source Channels 2 and 3 are separate 8-bit PWMs Channels 2 and 3 are concatenated to create one 16-bit PWM channel. For More Information On This Product, MC68HC912BL16TS/D CLOCK 8-BIT DOWN COUNTER PWSCNT0 ...
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... For More Information On This Product, 70 NOTE PCKA1 PCKA0 Value of (PCKB1) (PCKB0) Clock A ( 128 PCLK0 PPOL3 PPOL2 to: www.freescale.com $0041 1 Bit 0 PPOL1 PPOL0 0 0 MC68HC912BL16 MC68HC912BL16TS/D ...
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... Read and write anytime. PWEN3 — PWM Channel 3 Enable The pulse modulated signal will be available at port P, bit 3 when its clock source begins its next cycle Channel 3 is disabled. For More Information On This Product, MC68HC912BL16TS/D NOTE NOTE ...
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... Go to: www.freescale.com $0043 1 Bit 0 1 Bit $0044 1 Bit 0 1 Bit $0045 1 Bit 0 1 Bit $0046 1 Bit 0 1 Bit MC68HC912BL16 MC68HC912BL16TS/D ...
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... To start a new period immediately, write the new pe- riod value and then write the counter forcing a new period to start with the new period value. Period = Channel-Clock-Period Period = Channel-Clock-Period For More Information On This Product, MC68HC912BL16TS ...
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... PSWAI CENTR RDP to: www.freescale.com 1 Bit 0 1 Bit 0 $0050 1 Bit 0 $0051 1 Bit 0 $0052 1 Bit 0 $0053 1 1 (PPOLx = 1) (PPOLx = 0) (PPOLx = 0) (PPOLx = 1) $0054 1 Bit 0 PUPP PSBCK 0 0 MC68HC912BL16 MC68HC912BL16TS/D ...
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... Writes do not change pin state when pin is configured for PWM outputs, only after the PWM channel becomes available on port P pin, see PWEN bit description. PORTPD — Port P Data Direction Register Bit 7 6 DDP7 DDP6 DDP5 RESET For More Information On This Product, MC68HC912BL16TS ...
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... The boundary conditions for the PWM channel duty registers and the PWM channel period registers cause these results: Table 24 PWM Boundary Conditions PWDTYx $FF $FF PWPERx PWPERx – – For More Information On This Product, 76 PWPERx PPOLx Output $00 1 Low $00 0 High – 1 High – 0 Low $00 1 High $00 0 Low Go to: www.freescale.com MC68HC912BL16 MC68HC912BL16TS/D ...
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... The standard timer module consists of a 16-bit software-programmable counter driven by a prescaler. It contains seven complete 16-bit input capture/output compare channels and one 16-bit pulse accumu- lator. (Port T[6] is not bonded to any pin in MC68HC912BL16.) This timer can be used for many purposes, including input waveform measurements while simulta- neously generating an output waveform ...
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... Read anytime but will always return $00 (1 state is transient). Write anytime. Port T[6] is not bonded out to any pin in MC68HC912BL16. FOC[7:0] — Force Output Compare Action for Channel 7-0 A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare “ ...
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... Read or write anytime. Port T[6] is not bonded to any pin in MC68HC912BL16. The bits of OC7D correspond bit-for-bit with the bits of timer port (PORTT). When a successful OC7 compare occurs, for each bit that is set in OC7M, the corresponding data bit in OC7D is stored to the corresponding bit of the timer port. ...
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... RESET Read or write anytime. Port T[6] is not bonded to any pin in MC68HC912BL16. OMn — Output Mode OLn — Output Level These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCn compare. When either OMn or OLn is one, the pin associated with OCn becomes an output tied to OCn regardless of the state of the associated DDRT bit ...
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... Bit 7 6 EDG3B EDG3A EDG2B RESET Read or write anytime. Port T[6] is not bonded to any pin in MC68HC912BL16. EDGnB, EDGnA — Input Capture Edge Control These eight pairs of control bits configure the input capture edge detector circuits. Table 26 Edge Detector Circuit Configuration EDGnB TMSK1 — ...
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... PR0 Factor Reserved 1 1 Reserved C4F C3F C2F to: www.freescale.com $008E 1 Bit 0 C1F C0F 0 0 $008F 1 Bit MC68HC912BL16 MC68HC912BL16TS/D ...
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... Bit 7 6 TC5 — Timer Input Capture/Output Compare Register 5 Bit 7 6 Bit 15 14 Bit 7 6 TC6 — Timer Input Capture/Output Compare Register 6 Bit 7 6 Bit 15 14 Bit 7 6 For More Information On This Product, MC68HC912BL16TS ...
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... Read anytime. Write anytime for output compare function. Writes to these registers have no meaning or effect during input capture. All timer input capture/output compare registers are reset to $0000. Port T[6] is not bonded to any pin in MC68HC912BL16. PACTL — Pulse Accumulator Control Register Bit 7 ...
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... TCBYP — Timer Divider Chain Bypass 0 = Normal operation 1 = The 16-bit free-running timer counter is divided into two 8-bit halves and the prescaler is by- passed. The clock drives both halves directly. PCBYP — Pulse Accumulator Divider Chain Bypass For More Information On This Product, MC68HC912BL16TS ...
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... The minimum pulse width for the input capture should always be greater than the width of two module clocks due to input synchronizer circuitry. Port T[6] is not bonded to any pin in MC68HC912BL16. DDRT — Data Direction Register for Timer Port Bit 7 ...
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... Figure 21 Serial Interface Block Diagram 13.2 Serial Communication Interface (SCI) The serial communication interface on the MC68HC912BL16 is an NRZ format (one start, eight or nine data, and one stop bit) asynchronous communication system with independent internal baud rate gen- eration circuitry and an SCI transmitter and receiver. It can be configured for eight or nine data bits (one of which may be designated as a parity bit, odd or even) ...
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... TxMTR CONTROL SC0CR2/SCI CTL 2 SC0SR1/INT STATUS INT REQUEST LOGIC SCI RECEIVER DATA RECOVERY MSB 10-11 BIT SHIFT REG RxD BUFFER/SC0DRL WAKE-UP LOGIC SC0SR1/INT STATUS SC0CR2/SCI CTL 2 INT REQUEST LOGIC Go to: www.freescale.com LSB TxD PS1 RxD PS0 LSB HC12B32 SCI BLOCK MC68HC912BL16 MC68HC912BL16TS/D ...
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... The baud rate generator is disabled until the bit in SC0CR2 register is set for the first time after reset, and/or the baud rate generator is disabled when SBR[12: For More Information On This Product, MC68HC912BL16TS/D Table 29 Baud Rate Generation BR Divisor for BR Divisor for P = 4.0 MHz ...
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... Single wire mode without TXD output (the pin is used as receiver input only, TXD = High Impedance) Single wire mode with TXD output (the output is also fed back to receiver input, CMOS) Single wire mode for the receiving and transmitting (open-drain) Go to: www.freescale.com $00C2 1 Bit MC68HC912BL16 MC68HC912BL16TS/D ...
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... SCI transmit logic is enabled and the TXD pin (port S bit 1) is dedicated to the transmitter. The TE bit can be used to queue an idle preamble. RE — Receiver Enable 0 = Receiver disabled 1 = Enables the SCI receive circuitry For More Information On This Product, MC68HC912BL16TS RIE ILIE ...
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... New byte is ready to be transferred from the receive shift register to the receive data register and the receive data register is already full (RDRF bit is set). Data transfer is inhibited until this bit is cleared overrun 1 = Overrun detected For More Information On This Product IDLE to: www.freescale.com $00C4 1 Bit MC68HC912BL16 MC68HC912BL16TS/D ...
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... This bit is the ninth serial data bit transmitted when the SCI system is configured for nine-data-bit oper- ation. When using 9-bit data format this bit does not have to be written for each data word. The same value will be transmitted as the ninth bit until this bit is rewritten. For More Information On This Product, MC68HC912BL16TS ...
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... Serial Peripheral Interface (SPI) The serial peripheral interface allows the MC68HC912BL16 to communicate synchronously with pe- ripheral devices and other microprocessors. The SPI system in the MC68HC912BL16 can operate as a master slave. The SPI is also capable of interprocessor communications in a multiple master system. ...
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... SPI system. The CPOL bit simply selects non-in- verted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by shifting the clock by one half cycle or no phase shift. For More Information On This Product, MC68HC912BL16TS/D 8-BIT SHIFT REGISTER READ DATA BUFFER SP0DR SPI DATA REGISTER ...
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... Bit 3 Bit 4 Bit 5 Go to: www.freescale.com End Bit 1 LSB Minimum 1/2 SCK for Bit 6 MSB HC12 SPI CLOCK FORM 0 End Bit 1 LSB Minimum 1/2 SCK for Bit 6 MSB HC12 SPI CLOCK FORM 1 MC68HC912BL16 MC68HC912BL16TS/D ...
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... Operating Modes and Resource Mapping. SP0CR1 — SPI Control Register 1 Bit 7 6 SPIE SPE SWOM RESET For More Information On This Product, MC68HC912BL16TS/D Table 31 SS Output Selection Master Mode SS Input with MODF Feature Reserved General-Purpose Output SS Output MO Serial In SPI MI Serial Out SWOM enables open drain output ...
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... Halt SSI clock generation when in wait mode SPC0 — Serial Pin Control 0 This bit decides serial pin configurations with MSTR control bit. For More Information On This Product to: www.freescale.com $00D1 1 Bit 0 SSWAI SPC0 0 0 MC68HC912BL16 MC68HC912BL16TS/D ...
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... WCOL — Write Collision Status Flag The MCU write is disabled to avoid writing over the data being transferred. No interrupt is generated because the error status flag can be read upon completion of the transfer that was in progress at the For More Information On This Product, MC68HC912BL16TS/D 2 MSTR MISO ...
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... PS4 PS3 PS2 MISO N/A N/A SISO DDS4 DDS3 DDS2 to: www.freescale.com $00D5 1 Bit 0 1 Bit $00D6 1 Bit 0 PS1 PS0 TXD0 RXD0 $00D7 1 Bit 0 DDS1 DDS0 0 0 MC68HC912BL16 MC68HC912BL16TS/D ...
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... DDS2, DDRS3 — Data Direction for Port S Bit 2 and Bit 3 Port S[3:2] are not bonded out to any pin in MC68HC912BL16. DDS[6:4] — Data Direction for Port S Bits 6 through 4 If the SPI is enabled and expects the corresponding port S pin input, it will be an input regard- less of the state of the DDRS bit ...
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... PUPS0 — Pull-Up Port S Enable PS[1: internal pull-ups on port S bits 1 and Port S input pins for bits 1 and 0 have an active pull-up device pin is programmed as output, the pull-up device becomes inactive. For More Information On This Product, 102 Go to: www.freescale.com MC68HC912BL16 MC68HC912BL16TS/D ...
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... Freescale Semiconductor, Inc. For More Information On This Product, MC68HC912BL16TS/D Go to: www.freescale.com 103 ...
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... DATA INPUT REGISTER ATD 5 ATD 6 CLOCK ATD 7 SELECT/PRESCALE INTERNAL BUS to: www.freescale.com V RH REFERENCE DDA SUPPLY V SSA AN7/PAD7 AN6/PAD6 AN5/PAD5 AN4/PAD4 AN3/PAD3 AN2/PAD2 AN1/PAD1 AN0/PAD0 HC12 ATD BLOCK $0060 1 Bit MC68HC912BL16 MC68HC912BL16TS/D ...
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... FRZ1, FRZ0 — Background Debug (Freeze) Enable (suspend module operation at breakpoint) When debugging an application useful in many cases to have the ATD pause when a breakpoint is encountered. These two bits determine how the ATD will respond when background debug mode be- comes active. For More Information On This Product, MC68HC912BL16TS ...
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... Total 8-bit Conversion Time Total 10-bit Conversion Time 18 ATD clock periods 20 ATD clock periods 24 ATD clock periods 32 ATD clock periods Go to: www.freescale.com $0064 1 Bit 0 PRS1 PRS0 ATD clock periods 22 ATD clock periods 26 ATD clock periods 34 ATD clock periods MC68HC912BL16 MC68HC912BL16TS/D ...
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... ATD sequencer runs all four or eight conversions on a single input channel selected via the CD, CC, CB, and CA bits ATD sequencer runs each of the four or eight conversions on sequential channels in a specific group. Refer to Table 36. CD, CC, CB, and CA — Channel Select for Conversion For More Information On This Product, MC68HC912BL16TS/D Table 35 Clock Prescaler Values 1 Max P Clock 4 MHz 8 MHz ...
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... TEST/Reserved Go to: www.freescale.com if MULT = 1 ADR0 ADR1 ADR2 ADR3 ADR0 ADR1 ADR2 ADR3 ADR0 ADR1 ADR2 ADR3 ADR0 ADR1 ADR2 ADR3 ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 MC68HC912BL16 MC68HC912BL16TS/D ...
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... Reads of this byte return the current value in the SAR. Writes to this byte change the SAR to the value written. Bits SAR[9:2] reflect the eight SAR bits used during the resolution process for an 8-bit result. Bits SAR[9:0] reflect the eight SAR bits used during the resolution process for an 10-bit result For More Information On This Product, MC68HC912BL16TS ...
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... Go to: www.freescale.com $006F 1 Bit 0 PAD1 PAD0 – – specifi $0070 $0071 $0072 $0073 $0074 $0075 $0076 $0077 $0078 $0079 $007A $007B $007C $007D $007E $007F 9 Bit – – MC68HC912BL16 MC68HC912BL16TS/D ...
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... BDM — Debug options available as set in register ATDCTL3. USER — ATD continues running unless ADPU is cleared. ADPU — ATD operations are stopped if ADPU = 0, but registers are accessible. For More Information On This Product, MC68HC912BL16TS/D ) before initiating a new ATD conversion sequence to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, 112 Go to: www.freescale.com MC68HC912BL16 MC68HC912BL16TS/D ...
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... Freescale Semiconductor, Inc. 15 Development Support Development support involves complex interactions between MC68HC912BL16 resources and exter- nal development systems. The following section concerns instruction queue and queue tracking sig- nals, background debug mode, breakpoints, and instruction tagging. 15.1 Instruction Queue It is possible to monitor CPU activity on a cycle-by-cycle basis for debugging.The CPU12 instruction queue provides at least three bytes of program information to the CPU when instruction execution be- gins ...
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... MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 PERCEIVED START OF BIT TIME SYNCHRONIZATION UNCERTAINTY Figure 28 BDM Host to Target Serial Bit Timing For More Information On This Product, 114 TARGET SENSES BIT 10 CYCLES Go to: www.freescale.com EARLIEST START OF NEXT BIT HC12A4 BDM HOST TO TARGET TIM MC68HC912BL16 MC68HC912BL16TS/D ...
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... BKGD PIN Figure 29 BDM Target to Host Serial Bit Timing (Logic 1) Figure 29 shows the host receiving a logic one from the target MC68HC912BL16 MCU. Since the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target E cycles) ...
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... BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target MC68HC912BL16 finishes it. Since the target wants the host to receive a logic zero, it drives the BKGD pin low for 13 E-clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about ten cycles after starting the bit time ...
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... BDM is active. The CPU executes code from this ROM to perform the requested operation. The BDM firmware watches for serial commands and executes them as they are received. The firmware commands are shown in Table 39. For More Information On This Product, MC68HC912BL16TS/D Data None Enter background mode (if firmware enabled). ...
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... Write D accumulator 16-bit data in Write X index register 16-bit data in Write Y index register 16-bit data in Write stack pointer None Go to user program None Execute one user instruction then return to BDM None Enable tagging and go to user program Go to: www.freescale.com MC68HC912BL16 MC68HC912BL16TS/D ...
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... No data 1 = Data included in command R/W — Read/Write Flag 0 = Write 1 = Read BKGND — Hardware request to enter active background mode For More Information On This Product, MC68HC912BL16TS/D Table 40 BDM registers Register BDM Instruction Register BDM Status Register BDM Shift Register BDM Address Register BDM CCR Holding Register ...
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... For More Information On This Product, 120 TTAGO Table 41 TTAGO Decoding TTAGO Value Instruction 00 — TRACE1 11 TAGGO Table 42 REGN Decoding REGN Value Instruction 000 — 001 — 010 READ/WRITE NEXT 011 PC Go to: www.freescale.com (BDM) $FF00 1 Bit 0 REGN 0 0 MC68HC912BL16 MC68HC912BL16TS/D ...
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... SDV — Shifter Data Valid Shows that valid data is in the serial interface shift register. Used by BDM firmware valid data 1 = Valid Data TRACE — Asserted by the TRACE1 instruction For More Information On This Product, MC68HC912BL16TS/D Table 42 REGN Decoding REGN Value Instruction 100 D ...
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... BDM firmware. The register is initialized by the firmware to equal the CPU CCR register. 15.3 Breakpoints Hardware breakpoints are used to debug software on the MC68HC912BL16 by comparing actual ad- dress and data values to predetermined data in setup registers. A successful comparison will place the CPU in background debug mode (BDM) or initiate a software interrupt (SWI). Breakpoint features de- signed into the MC68HC912B32 include: • ...
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... The scope of comparison can be limited to program data only by setting the BKPM bit in breakpoint con- trol register 0. To trace program flow, setting the BKPM bit causes address comparison of program data only. Control bits are also available that allow checking read/write matches. For More Information On This Product, MC68HC912BL16TS/D Go to: www.freescale.com 123 ...
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... Upper 8-bit address only for dual mode BKP1 Full 16-bit address for dual mode BKP1 BKMBL BK1RWE BK1RW to: www.freescale.com $0020 1 Bit R/W Range — — — No Yes Yes Yes Yes Yes $0021 1 Bit 0 BK0RWE BK0RW 0 0 MC68HC912BL16 MC68HC912BL16TS/D ...
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... For More Information On This Product, MC68HC912BL16TS/D BK0RW Read/Write Selected R/W is don’t care for full mode or dual mode 0 X BKP0 1 0 R/W is write for full mode or dual mode BKP0 1 1 R/W is read for full mode or dual mode BKP0 – ...
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... NOTE Go to: www.freescale.com $0022 1 Bit 0 9 Bit $0023 1 Bit 0 1 Bit $0024 1 Bit 0 9 Bit $0025 1 Bit 0 1 Bit MC68HC912BL16 MC68HC912BL16TS/D ...
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... The tag follows the information in the queue as the queue is advanced. When a tagged instruction reaches the head of the queue, the CPU enters active background debugging mode rather than exe- cuting the instruction. This is the mechanism by which a development system initiates hardware break- points. For More Information On This Product, MC68HC912BL16TS/D Table 46 Tag Pin Function TAGLO Tag 1 ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Go to: www.freescale.com MC68HC912BL16 MC68HC912BL16TS/D ...